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S3C72G9 Datasheet(PDF) 9 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 9 Page - Samsung semiconductor |
9 / 96 page ![]() Table 5-9. CPU Control Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles SCF – Set carry flag to logic one 1 1 RCF Reset carry flag to logic zero 1 1 CCF Complement carry flag 1 1 EI Enable all interrupts 2 2 DI Disable all interrupts 2 2 IDLE Engage CPU idle mode 2 2 STOP Engage CPU stop mode 2 2 NOP No operation 1 1 SMB n Select memory bank 2 2 SRB n Select register bank 2 2 REF memc Reference code 1 3 VENTn EMB (0,1) ERB (0,1) ADR Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location 2 2 Table 5-10. Program Control Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles CPSE R,#im Compare and skip if register equals #im 2 2 + S @HL,#im Compare and skip if indirect data memory equals #im 2 2 + S A,R Compare and skip if A equals R 2 2 + S A,@HL Compare and skip if A equals indirect data memory 1 1 + S EA,@HL Compare and skip if EA equals indirect data memory 2 2 + S EA,RR Compare and skip if EA equals RR 2 2 + S LJP ADR Long jump to direct address (15 bits) 3 3 JP ADR Jump to direct address (14 bits) 3 3 JPS ADR Jump direct in page (12 bits) 2 2 JR #im Jump to immediate address 1 2 @WX Branch relative to WX register 2 3 @EA Branch relative to EA 2 3 LCALL ADR Long call direct in page (15 bits) 3 4 CALL ADR Call direct in page (14 bits) 3 4 CALLS ADR Call direct in page (11 bits) 2 3 RET – Return from subroutine 1 3 IRET – Return from interrupt 1 3 SRET – Return from subroutine and skip 1 3 + S |
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