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S3C72G9 Datasheet(PDF) 90 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 90 Page - Samsung semiconductor |
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90 / 96 page  %$$'! % STOP Operation: Operand Operation Summary Bytes Cycles – Engage CPU stop mode 2 2 Description: The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Operand Binary Code Operation Notation – 1 1 1 1 1 1 1 1 PCON.3 ← 1 1 0 1 1 0 0 1 1 Example: Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception of some peripheral hardware). The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed. |
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Similar Description - S3C72G9 |
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