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S3C72G9 Datasheet(PDF) 91 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 91 Page - Samsung semiconductor |
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91 / 96 page  %66'+ %!!',, VENTn dst Operation: Operand Operation Summary Bytes Cycles EMB (0,1) ERB (0,1) ADR Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location. 2 2 Description: The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine. The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These starting addresses must be located in ROM ranges 0000H-3FFFH. Generally, the VENTn instructions are coded starting at location 0000H. The format for VENT instructions is as follows: VENTn d1,d2,ADDR EMB ← d1 ("0" or "1") ERB ← d2 ("0" or "1") PC ← ADDR (address to branch n = device-specific module address code (n = 0-n) Operand Binary Code Operation Notation EMB (0,1) ERB (0,1) ADR E M B E R B a13 a12 a11 a10 a9 a8 ROM (2 x n) 7-6 → EMB, ERB ROM (2 x n) 5-4 → PC13-12 ROM (2 x n) 3-0 → PC11-8 ROM (2 x n + 1) 7-0 → PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0 |
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