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S3C72G9 Datasheet(PDF) 95 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 95 Page - Samsung semiconductor |
95 / 96 page ![]() /+ *'+!'2' XCHI dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Exchange A and data memory contents; increment contents of register L and skip on overflow 1 2 + S Description: The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L. If the content of register L is 0H, a skip is executed. The value of the carry flag is unaffected. Operand Binary Code Operation Notation A,@HL 0 1 1 1 1 0 1 0 A ↔ (HL), then L ← L+1; skip if L = 0H Example: Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH: LD HL,#2FH LD A,#0H XCHI A,@HL ; A ← 0FH and L ← L + 1 = 0, (HL) ← "0" JPS XXX ; Skipped since an overflow occurred JPS YYY ; H ← 2H, L ← 0H YYY XCHI A,@HL ; (20H) ← 0FH, A ← (20H), L ← L + 1 = 1H The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction. |
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