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TMS320LC2402A Datasheet(PDF) 110 Page - Texas Instruments |
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TMS320LC2402A Datasheet(HTML) 110 Page - Texas Instruments |
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110 / 133 page  TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS SPRS145J − JULY 2000 − REVISED NOVEMBER 2004 110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Flash parameters @40 MHz CLOCKOUT† PARAMETER MIN TYP MAX UNIT ‡ Time/Word (16-bit) 30 µs Clear/Programming time‡ Time/4K Sector 130 ms Clear/Programming time‡ Time/12K Sector 400 ms Erase time‡ Time/4K Sector 350 ms Erase time‡ Time/12K Sector 1 s ICCP (VCCP pin current) Indicates the typical/maximum current consumption during the Clear-Erase-Program (C-E-P) cycle 5 15 mA † TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change. ‡ The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance could also impact the timing parameters. migrating from LF240xA (Flash) devices to LC240xA (ROM) devices Table 18 outlines the differences between the LF240xA (Flash) devices and the LC240xA (ROM) devices. These differences should be taken into consideration when migrating between the devices. Table 18. Differences Between LF240xA (Flash) Devices and LC240xA (ROM) Devices FEATURE LF2406A LC2406A LC2404A LF2403A LF2402A LC2402A On-chip Flash or ROM 32K 32K 16K 16K 8K 6K Single-Access RAM (SARAM) (16-bit words) 2K 2K 1K 512 512 — Boot ROM Yes — — Yes Yes — Event Managers EVA, EVB EVA, EVB EVA, EVB EVA EVA EVA ADC Channels 16 16 16 8 8 8 SPI Yes Yes Yes Yes§ — — CAN Yes Yes — Yes — — GPIO Pins 41 41 41 21 21 21 BIO Pin Yes Yes Yes — — — TDIRx Pin Yes Yes Yes — — — External Interrupts 5 5 5 3 3 3 Access to External Memory Spaces (NOTE: Application code should NOT access Illegal/Reserved addresses.) See Note 3 See Note 4 See Note 4 See Note 3 See Note 3 See Note 4 VCCP Pin Functionality VCCP No Connect No Connect VCCP VCCP No Connect Packaging 100-pin PZ 100-pin PZ 100-pin PZ 64-pin PAG 64-pin PG 64-pin PG, PAG § The SPISTE pin is not available on the LF2403A. See the SPI Slave Mode Operation in LF2403A section. NOTES: 3. Access to external Program, Data, and I/O space is considered illegal and would assert an NMI. 4. The external Program and I/O spaces are implemented as “reserved” addresses and any access will not assert an NMI. However, the external data memory space is illegal. |
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