REV. A

AD974

–7–

CONVERSION CONTROL

The AD974 is controlled by two signals: R/

C and CS. When

R/

C is brought low, with CS low, for a minimum of 50 ns, the

input signal will be held on the internal capacitor array and a

conversion “n” will begin. Once the conversion process does

begin, the

BUSY signal will go low until the conversion is com-

plete. Internally, the signals R/

C and CS are ORed together and

there is no requirement on which signal is taken low first when

initiating a conversion. The only requirement is that there be at

least 10 ns of delay between the two signals being taken low.

After the conversion is complete, the

BUSY signal will return

high and the AD974 will again resume tracking the input signal.

Under certain conditions the

CS pin can be tied Low and R/C

will be used to determine whether you are initiating a conver-

sion or reading data. On the first conversion, after the AD974 is

powered up, the DATA output will be indeterminate.

Conversion results can be clocked serially, using either an

internal clock generated by the AD974 or an external clock.

The AD974 is configured for the internal data clock mode by

pulling the EXT/

INT pin low. It is configured for the external

clock mode by pulling the EXT/

INT pin high.

INTERNAL DATA CLOCK MODE

The AD974 is configured to generate and provide the data clock

when the EXT/

INT pin is held low. Typically CS will be tied

low and R/

C will be used to initiate a conversion “n.” During

the conversion the AD974 will output 16 bits of data, MSB first,

from conversion “n-1” on the DATA pin. This data will be

synchronized with 16 clock pulses provided on the DATACLK

pin. The output data will be valid on both the rising and falling

edge of the data clock as shown in Figure 3. After the LSB has

been presented, the DATACLK pin will stay low until another

conversion is initiated.

In this mode, the digital input/output pins’ transitions are suit-

ably positioned to minimize degradation on the conversion

result, mainly during the second half of the conversion process.

EXTERNAL DATA CLOCK MODE

The AD974 is configured to accept an externally supplied data

clock when the EXT/

INT pin is held high. This mode of opera-

tion provides several methods by which conversion results can

be read. The output data from conversion “n-1” can be read

during conversion “n,” or the output data from conversion “n”

CS, R/C

BUSY

MODE

ACQUIRE

CONVERT

CONVERT

ACQUIRE

A0, A1

WR1, WR2

Figure 2. Basic Conversion Timing

R/

C

DATACLK

DATA

BUSY

1

MSB

VALID

BIT 14

VALID

2

3

15

16

BIT 13

VALID

BIT 1

VALID

LSB

VALID

Figure 3. Serial Data Timing for Reading Previous Conversion Results with Internal Clock

(

CS and EXT/ INT Set to Logic Low)