AD9260ASZ datasheet(25/45 Pages) AD

25 / 45 page

AD9260

Rev. C | Page 24 of 44

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 60, a simplified model of the AD9260, highlights the

relationship between the analog inputs, VINA, VINB and the

reference voltage VREF. Like the voltage applied to the top of

the resistor ladder in a flash A/D converter, the value VREF

defines the maximum input voltage to the A/D converter. An

internal reference buffer in the AD9260 scales the reference

voltage VREF before it is applied internally to the AD9260 A/D

core. The scale factor of this reference buffer is 0.8.

Consequently, the maximum input voltage to the A/D core is

+0.8 × VREF. The minimum input voltage to the A/D core is

automatically defined to be –0.8 × VREF. With this scale factor,

the maximum differential input span of 4 V p-p is obtained

with a VREF voltage of 2.5 V. A smaller differential input span

may be obtained by using a VREF voltage of less than 2.5 V at

the expense of ac performance (refer to Figure 52).

A/D CORE

–0.8

× VREF

+0.8

× VREF

–

VINA

VINB

Figure 60. Simplified Input Model

INPUT SPAN

The AD9260 is implemented with a differential input structure.

This structure allows the common-mode level (average voltage

of the two input pins) of the input signal to be varied

independently of the input span of the converter over a wide

range, as shown in Figure 50. Specifically, the input to the A/D

core is the difference of the voltages applied at the VINA and

VINB input pins. Therefore, the equation,

VINB

VINA

VCORE

−

(1)

defines the output of the differential input stage and provides

the input to the A/D core.

The voltage, VCORE, must satisfy the condition,

VREF

VCORE

VREF

≤

−

(2)

where VREF is the voltage at the VREF pin.

INPUT COMPLIANCE RANGE

In addition to the limitations on the differential span of the

input signal indicated in Equation 2, an additional limitation is

placed on the inputs by the analog input structure of the

AD9260. The analog input structure bounds the valid operating

range for VINA and VINB. The condition,

AVDD

VINB

AVSS

AVDD

VINA

AVSS

−

(3)

where AVSS is nominally 0 V and AVDD is nominally +5 V,

defines this requirement. Thus the valid inputs for VINA and

VINB are any combination that satisfies both Equations 2 and 3.

Note that the clock clamping method used in the differential

driver circuit shown in Figure 63 is sufficient for protecting the

AD9260 in an undervoltage condition.

For additional information showing the relationships between

VINA, VINB, VREF, and the digital output of the AD9260, see

Table 13.

Refer to Table 12 for a summary of the various analog input and

reference configurations.

ANALOG INPUT OPERATION

The analog input structure of the AD9260 is optimized to meet

the performance requirements for some of the most demanding

communication and data acquisition applications. This input

structure is composed of a switched-capacitor network that

samples the input signal applied to pins VINA and VINB on

every rising edge of the CLK pin. The input switched capacitors

are charged to the input voltage during each period of CLK. The

resulting charge, q, on these capacitors is equal to C × VIN,

where C is the input capacitor. The change in charge on these

capacitors, delta q, as the capacitors are charged from a previous

sample of the input signal to the next sample, is approximated

in the following equation,

(

)

−

deltaV

delta

(4)

where VN represents the present sample of the input signal and

VN–2 represents the sample taken two clock cycles earlier. The

average current flow into the input (provided from an external

source) is given in the following equation,

(

)

CLOCK

delta

−

−2

(5)

where T represents the period of CLK and fCLOCK represents the

frequency of CLK. Equations 4 and 5 provide simplifying

approximations of the operation of the analog input structure of

the AD9260. A more exact, detailed description and analysis of

the input operation follows.

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