Data Sheet S16472EJ1V0DS

7

µµµµ PD16347

3. PIN FUNCTIONS

Symbol

Pin Name

I/O

Description

/LBLK

Low blanking

Input

/LBLK

= L: All output = L

/HBLK

High blanking

Input

/HBLK

= L: All output = H

/LE

Latch enable

Input

Latch operation performed at the falling edge.

HZ

Output high impedance

Input

HZ = H: All output set to the high-impedance state

/CLR

Register clear

Input

/CLR = L: All shift register data cleared to the low level

Data

Input

inside the R,/L pin.

CLK

Clock

Input

SDS = H: Shift operation is executed at the rising and falling edges

SDS = L: Shift operation is executed at the rising edge

R,/L

Shift direction control

Input

The shift direction control pin of shift register. The shift directions of the

shift register are as follows.

R,/L = H (right shift):

R,/L = L (left shift):

Refer to 5. INTERNAL REGISTER.

IBS1,

IBS2

Input mode switch

Input

IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, Length of shift register: 32-bit

IBS1 = H, IBS2 = L: 6-bit input, Length of shift register: 32-bit

IBS1 = L, IBS2 = H: 3-bit input, Length of shift register: 64-bit

IBS1 = L, IBS2 = L: 4-bit input, Length of shift register: 48-bit

DET

Temperature detection

Output

The DET is N-ch open-drain output. Low level is output (N-ch transistor:

ON) via temperature detection.

SDS

Clock edge switch

Input

SDS = H: Shift operation is executed at the rising and falling edges of CLK

(double edge)

SDS = L: Shift operation is executed at the rising edge of CLK (single edge)

High withstanding voltage

Output

70 V

Logic power supply

−

5 V

± 5%

Driver power supply

−

15 to 70 V

Temperature detection

power supply

−

5 V

± 10%

Logic ground

−

Connect to system ground

Driver ground

−

Connect to system ground

Temperature detection

ground

−

Connect to system ground

Caution In 3-bit and 4-bit input mode, unused input pins must be held at the low level or high level.