2

AD7714

REV. C

–15–

CH2

CH1

CH0

AIN(+)

AIN(–)

Type

Calibration Register Pair

0

0

0

AIN1

AIN6

Pseudo Differential

Register Pair 0

0

0

1

AIN2

AIN6

Pseudo Differential

Register Pair 1

0

1

0

AIN3

AIN6

Pseudo Differential

Register Pair 2

0

1

1

AIN4

AIN6

Pseudo Differential

Register Pair 2

1

0

0

AIN1

AIN2

Fully Differential

Register Pair 0

1

0

1

AIN3

AIN4

Fully Differential

Register Pair 1

1

1

0

AIN5

AIN6

Fully Differential

Register Pair 2

1

1

1

AIN6

AIN6

Test Mode

Register Pair 2

Mode Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 00 Hex

The Mode Register is an eight bit register from which data can either be read or to which data can be written. Table VIII outlines the

bit designations for the Mode Register.

Table VIII. Mode Register

MD2

MD1

MD0

G2

G1

G0

BO

FSYNC

MD2

MD1

MD0

Operating Mode

0

0

0

Normal Mode; this is the normal mode of operation of the device whereby the device is performing nor-

mal conversions. This is the default condition of these bits after Power-On or

RESET.

0

0

1

Self-Calibration; this activates self-calibration on the channel selected by CH2, CH1 and CH0 of the

Communications Register. This is a one step calibration sequence and when complete the part returns to

Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The

DRDY output or bit goes high when

calibration is initiated and returns low when this self-calibration is complete and a new valid word is

available in the data register. The zero-scale calibration is performed at the selected gain on internally

shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally-

0

1

0

Zero-Scale System Calibration; this activates zero scale system calibration on the channel selected by

CH2, CH1 and CH0 of the Communications Register. Calibration is performed at the selected gain on

the input voltage provided at the analog input during this calibration sequence. This input voltage should

remain stable for the duration of the calibration. The

DRDY output or bit goes high when calibration is

initiated and returns low when this zero-scale calibration is complete and a new valid word is available in

the data register. At the end of the calibration, the part returns to Normal Mode with MD2, MD1 and

MD0 returning to 0, 0, 0.

0

1

1

Full-Scale System Calibration; this activates full-scale system calibration on the selected input channel.

Calibration is performed at the selected gain on the input voltage provided at the analog input during this

calibration sequence. This input voltage should remain stable for the duration of the calibration. Once

again, the

DRDY output or bit goes high when calibration is initiated and returns low when this full-scale

calibration is complete and a new valid word is available in the data register. At the end of the calibration,

the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0.

Table VII. Channel Selection

CH2–CH0

Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as

outlined in Table VII. There are three pairs of calibration registers on the part. In fully differential mode, the part

has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the

AD7714 has five input channels with some of the input channel combinations sharing calibration registers. With

CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as

a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN6

input should be connected to an external voltage within the allowable common-mode range for the part. The

Power-On or RESET status of these bits is 1,0,0 selecting the differential pair AIN1 and AIN2.