EVAL-AD7712EB datasheet(21/29 Pages) AD

21 / 29 page

REV. F

–20–

AD7712

DIGITAL INTERFACE

The AD7712’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7712 can access data from the output

write to the AD7712 can write data to the control register or the

calibration registers.

Two different modes of operation are available, optimized for

different types of interfaces where the AD7712 can act either as

master in the system (it provides the serial clock) or as slave (an

external serial clock can be provided to the AD7712). These

two modes, labeled self-clocking mode and external clocking

mode, are discussed in detail in the following sections.

Self-Clocking Mode

The AD7712 is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7712 provides the

serial clock signal used for the transfer of data to and from the

AD7712. This self-clocking mode can be used with processors

that allow an external device to clock their serial port, including

most digital signal processors and microcontrollers such as the

68HC11 and 68HC05. It also allows easy interfacing to serial

parallel conversion circuits in systems with parallel data com-

munication, allowing interfacing to 74XX299 universal shift

registers without any additional decoding. In the case of shift

registers, the serial clock line should have a pull-down resistor

instead of the pull-up resistor shown in Figures 11 and 12.

Read Operation

Data can be read from the output register, the control register, or

the calibration registers. A0 determines whether the data read

accesses data from the control register or from the output/calibra-

tion registers. This A0 signal must remain valid for the duration

of the serial read operation. With A0 high, data is accessed from

either the output register or from the calibration registers. With

A0 low, data is accessed from the control register.

The function of the

DRDY line is dependent on only the output

update rate of the device and the reading of the output data

DRDY goes low when a new data-word is available in

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the

DRDY line will

remain low. The output register will continue to be updated at

the output update rate, but

DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

word in the output register. If a new data-word becomes avail-

able to the output register while data is being read from the

output register,

DRDY will not indicate this and the new data-

word will be lost to the user.

DRDY is not affected by reading

from the control register or the calibration registers.

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low with DRDY high, no data trans-

fer will take place.

DRDY does not have any effect on reading

data from the control register or from the calibration registers.

Figure 11 shows a timing diagram for reading from the AD7712

in the self-clocking mode. This read operation shows a read

from the AD7712’s output data register. A read from the con-

trol register or calibration registers is similar, but, in these cases,

the

DRDY line is not related to the read function. Depending

on the output update rate, it can go low at any stage in the

control/calibration register read cycle without affecting the read

and its status should be ignored. A read operation from either

the control or calibration registers must always read 24 bits of

data from the respective register.

Figure 11 shows a read operation from the AD7712. For the

timing diagram shown, it is assumed that there is a pull-up

resistor on the SCLK output. With

DRDY low, the RFS input

is brought low.

RFS going low enables the serial clock of the

AD7712 and also places the MSB of the word on the serial data

line. All subsequent data bits are clocked out on a high to low

transition of the serial clock and are valid prior to the following

rising edge of this clock. The final active falling edge of SCLK

clocks out the LSB, and this LSB is valid prior to the final active

rising edge of SCLK. Coincident with the next falling edge of

SCLK,

DRDY is reset high. DRDY going high turns off the

SCLK and the SDATA outputs, which means that the data

hold time for the LSB is slightly shorter than for all other bits.

SDATA (O)

SCLK (O)

THREE-STATE

RFS (I)

A0 (I)

DRDY (O)

MSB

LSB

t10

Figure 11. Self-Clocking Mode, Output Data Read Operation

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