3

ATL25SeriesASIC

1414C–ASIC-08/02

Design

Atmel supports several major software systems for design with complete cell libraries, as well

as utilities for netlist verification, test vector verification and accurate delay simulations

Table 2. Design Systems Supported

Atmel’s ASIC design flow is structured to allow the designer to consolidate the greatest num-

ber of system components onto the same silicon chip, using widely available third-party design

tools. Atmel’s cell library reflects silicon performance over extremes of temperature, voltage

and process, and includes the effects of metal loading, interlevel capacitance, and edge rise

and fall times. The design flow includes clock tree synthesis to customer-specified skew and

latency goals. RC extraction is performed on the final design database and incorporated into

the timing analysis.

The ASIC design flow, shown on page 4, provides a pictorial description of the typical interac-

tion between Atmel’s design staff and the customer. Atmel will deliver design kits to support

the customer’s synthesis, verification, floorplanning and scan insertion activities. Leading-

edge tools from vendors such as Synopsys and Cadence are fully supported in our design

flow. In the case of an embedded array design, Atmel will conduct a design review with the

customer to define the partition of the embedded array ASIC and to define the location of the

memory blocks and/or cores so an underlayer layout model can be created.

Following database acceptance, automated test pattern generation (ATPG) is performed, if

required, on scan paths using Synopsys tools; the design is routed; and post-route RC data is

extracted. After post-route verification and a final design review, the design is taped out for

fabrication.

System

Tools

Version

Design

Systems, Inc.

Opus

NC Verilog

Pearl

Verilog-XL

BuildGates

4.46

3.3-s008

4.3-s095

3.3-s006

4.0-p003

Mentor

Graphics

®

ModelSim

Leonardo Spectrum

5.5e

2001.1d

Synopsys

®

Design Compiler

DFT Compiler – 1-Pass Test Synthesis

BSD Compiler – Boundary Scan Synthesis

TetraMax

PrimeTime

VCS

Floorplan Manager

™

01.01-SP1

01.08-SP1

01.08-SP1

01.08

01.08-SP1

5.2

01.08-SP1

Novas

Software, Inc.

®

Debussy

®

5.1

Silicon

Perspective

™

First Encounter

®

v2001.2.3