12

ATL25SeriesASIC

1414C–ASIC-08/02

Testability

Techniques

For complex designs involving blocks of memory and/or cores, careful attention must be given

to design-for-test techniques. The sheer size of complex designs requires the use of more effi-

cient testability techniques. Combinations of SCAN paths, multiplexed access to memory

and/or core blocks, and built-in self-test logic (in addition to functional test patterns) must be

employed to provide both the user and Atmel with the ability to test the finished product.

An example of a highly complex design could include a PLL for clock management or synthesis,

a microprocessor or DSP engine or both, SRAM to support the microprocessor or DSP engine,

and glue logic to support the interconnectivity of each of these blocks. The design of each of

these blocks must take into consideration the fact that the manufactured device will be tested on

a high-performance digital tester. Combinations of parametric, functional and structural tests,

defined for digital testers, should be employed to create a suite of manufacturing tests.

The type of block dictates the type of testability technique to be employed. The PLL will, by

construction, provide access to key nodes so that functional and/or parametric testing can be

performed. Since a digital tester must control all the clocks during the testing of an ASIC, pro-

visions must be made for the VCO to be bypassed. Atmel’s PLLs include a multiplexing

capability for just this purpose. The addition of a few pins will allow other portions of the PLL to

be isolated for test without impinging upon the normal functionality.

In a similar vein, access to microprocessor, DSP and SRAM blocks must be provided so that

controllability and observability of the inputs and outputs to the blocks are achieved with the

minimum amount of preconditioning. The ARM and MIPS microprocessors, AVR microcontrol-

ler and OakDSPCore/TeakDSPCore/PalmDSPCore digital signal processors all support

SCAN testing. SRAM blocks need to provide access to both address and data ports so that

comprehensive memory tests can be performed. Multiplexing I/O pins is a method for provid-

ing this accessibility.

The glue logic can be designed using full SCAN techniques to enhance its testability.

It should be noted that in almost all of these cases, the purpose of the testability technique is

to assure all embedded circuit blocks are functional. All of the techniques described above

should be considered supplemental to a set of patterns that exercise the functionality of the

design in its anticipated operating modes.

Table 6. I/O Buffer DC Characteristics

Symbol

Parameter

Test Condition

Typical

Units

C

IN

Capacitance, Input Buffer (die)

3.3V

2.4

pF

Capacitance, Output Buffer (die)

3.3V

5.6

pF

Capacitance, Bidirectional

3.3V

6.6

pF