3

4885A–AUDR–09/05

ATR4289

3.

Functional Description

The ATR4289 is controlled via the 2-wire bus. One module-address byte, two subaddress bytes

and five data bytes enable programming.

The module address contains a programmable address bit A 1, which (along with address select

input AS, pin 4), enables the operation of two ATR4289 devices in one system. If bit A 1 is iden-

tical with the status of the address select input AS, the chip is selected.

The subaddress determines which of the data bytes is transmitted first. If the subaddress of the

R divider is transmitted, the sequence of the next data bytes is DB 0 (Status), DB 1 and DB 2. If

the subaddress of the N divider is transmitted, the sequence of the next data bytes is DB 3 and

DB 4. The bit organization of the module address, subaddress and 5 data bytes is shown in

Table 7-1 on page 8.

Each transmission on the bus begins with the START condition and has to be ended by the

STOP condition (see Table 8-1 on page 8, “Transmission Protocol” ).

The integrated circuit ATR4289 has two separate inputs for the AM and FM oscillators. Pre-

amplified AM and FM signals are fed to the 16-bit R divider via the AM/FM switch. The AM/FM

switch is software controlled. Tuning steps can be selected by the 16-bit R divider.

Furthermore, the device provides a digital memory phase detector and two separate current

sources for the AM and FM amplifier (charge pump) as given in the Table “Electrical Character-

istics” on page 5. It allows independent gain adjustment, providing high current for high-speed

tuning and low current for stable tuning.