CD54HC40103F datasheet(8/14 Pages) TI

8 / 14 page

Test Circuits and Waveforms

FIGURE 2.

FIGURE 3.

FIGURE 4.

FIGURE 5.

FIGURE 6.

FIGURE 7.

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tTHL

tPHL

90%

10%

GND

tPLH

tTLH

INPUT LEVEL

1/fMAX

90%

10%

INPUT LEVEL

GND

tREM

GND

INPUT LEVEL

10%

90%

tPHL

tTHL

tTLH

tPLH

INPUT LEVEL

10%

90%

tSU

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUTS

P0 - P7

VALID

tSU

tREC

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUT LEVEL

GND

tSU

INPUT LEVEL

GND

INPUT LEVEL

GND

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

tWL

tWH

10%

tWL + tWH =

fCL

CLOCK

2.7V

1.3V

0.3V

GND

trCL = 6ns

tfCL = 6ns

1.3V

tWL

tWH

0.3V

tWL + tWH =

fCL

CD54HC40103, CD74HC40103, CD74HCT40103

CD54HC40103F Datasheet(PDF) 8 Page - Texas Instruments

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