SLG46120 datasheet(2/92 Pages) DIALOG

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000-0046120-108

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SLG46120

1.0 Overview

The SLG46120 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit

design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the

macrocells of the SLG46120. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a

very small, low power single integrated circuit. The macrocells in the device include the following:

•

Two Analog Comparators (ACMP)

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Voltage References (Vref)

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Five Combinatorial Look Up Tables (LUTs)

• One 2-bit LUTs

• Four 3-bit LUTs

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Twelve Combination Function Macrocell

• Four Selectable DFF/Latch or 2-bit LUTs

• Four Selectable DFF/Latch or 3-bit LUTs

• One Selectable Pipe Delay or 3-bit LUT

• Pipe Delay – 8 stage / 2 output, one 1 stage fixed output

• Two Selectable Counter/Delay or 4-bit LUT

• One Programmable Delay / Deglitch Filter

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Two Counter / Delay Generators (CNT/DLY)

• One 8-bit counter/delay

• One 14-bit counter/delay with external clock/reset

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Eight D Flip-Flop / Latches (DFF) (Part of Combination Function Macrocell)

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Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)

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One Bandgap

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RC Oscillator (RC OSC)

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Power On Reset (POR)

SLG46120 Datasheet(PDF) 2 Page - Dialog Semiconductor