SLG46538 datasheet(92/205 Pages) DIALOG

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SLG46538_DS_109

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SLG46538

Table 82. CNT/DLY4 Register Settings

Signal Function

Address

LUT3_7 or

Counter4 Select

reg<1196>

0: LUT3_7

1: Counter4

Delay4 Mode Select

or asynchronous

counter reset

reg<1289:1288> 00: on both falling and rising edges (for delay & counter reset)

01: on falling edge only (for delay & counter reset)

10: on rising edge only (for delay & counter reset)

11: no delay on either falling or rising edges / counter high level reset

Counter/delay4

Clock Source Select

reg<1292:1290> 000: Internal OSC clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: 25MHz OSC clock

110: External Clock

111: Counter3 Overflow

Counter/delay4

Output Selection for

Counter mode

reg<1293>

0: Default Output

1: Edge Detector Output

Counter/delay4

Mode Selection

reg<1295:1294> 00: Delay mode

01: One Shot

10: Freq. Detect

11: Counter mode

Counter/delay4

Control Data

reg<1559:1552> 1 - 255

Table 83. CNT/DLY5 Register Settings

Signal Function

Address

LUT3_8 or

Counter5 Select

reg<1195>

0: LUT3_8

1: Counter5

Delay5 Mode Select

or asynchronous

counter reset

reg<1297:1296> 00: on both falling and rising edges (for delay & counter reset)

01: on falling edge only (for delay & counter reset)

10: on rising edge only (for delay & counter reset)

11: no delay on either falling or rising edges / counter high level reset

Counter/delay5

Clock Source Select

reg<1300:1298> 000: Internal OSC clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: 25 MHz OSC clock

110: External Clock

111: Counter4 Overflow

Counter/delay5

Output Selection for

Counter mode

reg<1301>

0: Default Output

1: Edge Detector Output

Counter/delay5

Mode Selection

reg<1303:1302> 00: Delay mode

01: One Shot

10: Freq. Detect

11: Counter mode

Counter/delay5

Control Data

reg<1567:1560> 1 - 255

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