AD8284WCSVZ datasheet(21/29 Pages) AD

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AD8284

Data Sheet

Rev. D | Page 20 of 28

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: the

chip configuration registers map (Address 0x00 and Address 0x01),

the device index and transfer registers map (Address 0x04 to

Address 0xFF), and the ADC channel functions registers map

(Address 0x08 to Address 0x2C).

The leftmost column of the memory map indicates the register

address number, and the default value is shown in the second

rightmost column.

The Bit 7 (MSB) column is the start of the default hexadecimal

value that is given. For example, Address 0x09, the GLOBAL_

CLOCK register, has a default value of 0x01, meaning that Bit 7 = 0,

Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and

Bit 0 = 1, or 0000 0001 in binary. This setting is the default for

the duty cycle stabilizer in the on condition. By writing a 0 to

Bit 0 of this address followed by writing 0x01 to the SW transfer

bit in Register 0xFF, the duty cycle stabilizer is turned off. It is

important to follow each writing sequence with a write to the

SW transfer bit to update the SPI registers.

Caution

All registers except for Register 0x00 and Register 0xFF are

buffered with a master slave latch and require writing to the

transfer bit. For more information about this and other

functions, see the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI.

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “bit is cleared” is synonymous with “bit is set

to Logic 0” or “writing Logic 0 for the bit.

RESERVED LOCATIONS

Do not write to undefined memory except when writing the

default values suggested in this data sheet. Addresses that have

values marked as 0 should be considered reserved and have a 0

written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with

default values. These values are indicated in Table 10, where an

X refers to an undefined feature.

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