Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

SMSC LAN9115

5

Revision 0.1 (12-20-04)

PRODUCT PREVIEW

Figure 2 LAN9115 Internal Block Diagram

10/100

Ethernet

PHY

10/100

Ethernet

MAC

2kB to 14kB

Configurable TX FIFO

2kB to 14kB

Configurable RX FIFO

16-bit SRAM I/F

Interrupt

Controller

GP Timer

PIO Controller

IRQ

FIFO_SEL

3.3V to 1.8V

Regulator

PLL

25MHz

+3.3V

LAN

EEPROM

Controller

EEPROM

(Optional)

RX Status FIFO

TX Status FIFO

MIL - TX Elastic

Buffer - 2K bytes

MIL - RX Elastic

Buffer - 128 bytes

PME - Wakup Indicator

Host Bus Interface

(HBI)

Power Management

Optional

External PHY - MII Interface