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SN74LVC1G06DBVT Datasheet(PDF) 13 Page - Texas Instruments |
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SN74LVC1G06DBVT Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 41 page ![]() SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP 8 mil 8 mil 0402 0.1 …F Bypass Capacitor 8 mil WORST BETTER BEST 13 SN74LVC1G06 www.ti.com SCES295Z – JUNE 2000 – REVISED NOVEMBER 2017 Product Folder Links: SN74LVC1G06 Submit Documentation Feedback Copyright © 2000–2017, Texas Instruments Incorporated 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1- µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 8 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. An example layout is given in Figure 9 for the DPW (X2SON-5) package. This example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be used to trace out the center pin connection through another board layer, or it can be left out of the layout 11.2 Layout Example Figure 8. Trace Example Figure 9. Example Layout With DPW (X2SON-5) Package |
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