DS1640/DS1640C

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OPERATION

disconnected from its respective output based on the bias applied to the control gate (see Figure 1). A set

of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are

controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are

inverted and passed directly to the control gates, enabling the switches to be switched both independently

and asynchronously. With a transition from logic 0 to logic 1 on the latch pin, the input levels present on

the gate inputs are locked by the four internal latches, maintaining the corresponding FET gates at those

levels. As long as the latch input is maintained at logic 1, the FET gate levels are maintained. When the

latch input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates

without being latched. A TTL or CMOS logic 1 turns a switch completely on and TTL or CMOS logic 0

turns a switch completely off. The four switches can be operated independently or two or more can be

connected in parallel for added current carrying capability. The four switches contained within the

mode because the onboard charge pump is turned off. The gate and latch inputs are CMOS-compatible

DS1640 BLOCK DIAGRAM Figure 1