NE555 datasheet(3/6 Pages) HARRIS

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8-5

Schematic Diagram

Typical Applications

Reset Timer (Monostable Operation)

Figure 1 shows the CA555 connected as a reset timer. In this

mode of operation capacitor CT is initially held discharged by

a transistor on the integrated circuit. Upon closing the “start”

switch, or applying a negative trigger pulse to terminal 2, the

integral timer ﬂip-ﬂop is “set” and releases the short circuit

across CT which drives the output voltage “high” (relay ener-

gized). The action allows the voltage across the capacitor to

increase exponentially with the constant t = R1CT. When the

voltage across the capacitor equals 2/3 V+, the comparator

resets the ﬂip-ﬂop which in turn discharges the capacitor rap-

idly and drives the output to its low state.

Output Rise Time

100

Output Fall Time

100

NOTES:

2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.

3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total

R1 + R2 = 20MΩ.

Electrical Speciﬁcations

TA = 25

oC, V+ = 5V to 15V Unless Otherwise Speciﬁed (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

CA555, LM555

CA555C, LM555C, NE555

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

THRESHOLD

RESET

DISCHARGE

V-

RESET

DISCHARGE

OUTPUT

FLIP-FLOP

TRIGGER

COMPARATOR

THRESHOLD

COMPARATOR

4.7K

830

4.7K

10K

100

100K

Q11 Q12

Q10

Q13

Q16

Q14

Q15

Q17

3.9K

Q19

Q20

Q21

Q18

V+

CONTROL

VOLTAGE

6.8K

4.7K

220

4.7K

TRIGGER

NOTE: Resistance values are in ohms.

CA555, CA555C, LM555, LM555C, NE555

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