System description

STA1080, STA1085, STA1090, STA1095

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DocID028279 Rev 1

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System description

2.1

Processor MCU

Accordo2 family devices processing capability relies on an ARM Cortex-R4. The MCU has

instruction cache and data cache, as well as TCM Memory dedicated respectively to

instructions and data for high throughput and low latency tasks.

2.2

Memory controller

2.2.1

Embedded memory

Accordo2 family devices embed SRAM memory, which can be used for data or code

storage.

Embedded memory can be used in conjunction with executable in place NOR devices to

implement cost effective solutions. The whole embedded memory is also cacheable and

can be accessed by DMA.

2.2.2

SDRAM controller

SDRAM controller supports SDRAM JEDEC interface 16 bits wide, which allows interfacing

to automotive SDRAM memory devices to handle high footprint applications.

Such memory is cacheable, and can be accessed by DMA.

2.2.3

SQI executable in place

The SQIO controller allows interfacing Serial Quad I/O flash memories.

2.2.4

Parallel memory interface

FSMC static memory controller, provides a generic parallel interface suitable to connect to

NOR devices as well as SRAM and NAND devices. This peripheral allows execution in-

place from NOR/SRAMs, as well as DMA accesses.

NOR memory space can be partitioned so to reserve a portion of the parallel NOR device to

the Secure CAN Subsystem.

2.3

USB

Accordo2 family devices have one USB HS interface with embedded PHY, allowing to

efficiently connect to mass storage devices, as well as portable devices (phones, pads).

Along with USB connectivity, Accordo2 family fully support USB charger specification.

2.4

Sound subsystem

Accordo2 family devices implement a sound subsystem which allows to efficiently handle

sound processing tasks, such as spatialization and equalizer, without loading the main CPU

with interrupt intensive tasks.