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HT82V26 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc

Part # HT82V26
Description  16-Bit CCD/CIS Analog Signal Processor
PDF  16 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82V26 Datasheet(HTML) 4 Page - Holtek Semiconductor Inc

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Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
Temperature Range
tA
Operating
¾¾
0
¾
70
°C
Power Consumption
Ptot
Total Power Consumption
¾¾
¾
400
¾
mW
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
tPRA
3-channel pixel rate
100
¾¾
ns
tPRB
2-channel (Even-Odd) pixel rate
66
¾¾
ns
tPRC
1-channel pixel rate
40
¾¾
ns
tADCLK
ADCCLK Pulse Width
16
¾¾
ns
tC1
CDSCLK1 Pulse Width
12
¾¾
ns
tC2
CDSCLK2 Pulse Width
12
¾¾
ns
tC1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
¾¾
ns
tADC1
ADCCLK Rising to CDSCLK1 Falling
0
¾¾
ns
tADC2
ADCCLK Rising to CDSCLK2 Falling
0
¾¾
ns
tAD
Analog Sampling Delay
5
¾¾
ns
3-Channel Mode Only
taC2C1
CDSCLK2 Falling to CDSCLK1 Rising
30
¾¾
ns
taC2ADR
CDSCLK2 Falling to ADCCLK Rising
30
¾¾
ns
2-Channel Mode Only
tbC2ADR
CDSCLK2 Falling to ADCCLK Rising
30
¾¾
ns
tbC1ADR
CDSCLK1 Rising to ADCCLK Rising
15
¾¾
ns
tbC2C1
CDSCLK2 Falling to CDSCLK1 Rising
15
¾¾
ns
1-Channel Mode Only
tcC2C1
CDSCLK2 Falling to CDSCLK1 Rising
15
¾¾
ns
tcC1ADF
CDSCLK1 Rising to ADCCLK Falling
0
¾¾
ns
tcC2ADR
CDSCLK2 Falling to CDSCLK1 Rising
20
¾¾
ns
Serial Interface
fSCLK
Maximum SCLK Frequency
10
¾¾
MHz
tLS
SLOAD to SCLK Setup Time
10
¾¾
ns
tLH
SCLK to SLOAD Hold Time
10
¾¾
ns
tDS
SDATA to SCLK Rising Setup Time
10
¾¾
ns
tDH
SCLK Rising to SDATA Hold Time
10
¾¾
ns
tRDV
Falling to SDATA Valid
10
¾¾
ns
Data Output
tOD
Output Delay
¾
8
¾
ns
Latency (Pipeline Delay)
¾
9
¾
Cycles
HT82V26
Rev. 1.50
4
June 24, 2004



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