ST68C554 datasheet(20/40 Pages) EXAR

20 / 40 page

ST16C554/554D/68C554

Rev. 3.10

Transmit operation in mode 1:

When the 554D is in FIFO mode ( FCR bit-0 = logic 1,

FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1

when the transmit FIFO is completely full. It will be a

logic 0 if one or more FIFO locations are empty.

Receive operation in mode 1:

When the 554D is in FIFO mode (FCR bit-0 = logic 1,

FCR bit-3 = logic 1) and the trigger level has been

reached, or a Receive Time Out has occurred, the -

RXRDY pin will go to a logic 0. Once activated, it will

go to a logic 1 after there are no more characters in the

FIFO.

FCR BIT 4-5:

Not used - Initialized to a logic 0.

FCR BIT 6-7: (logic 0 or cleared is the default condi-

tion, Rx trigger level = 1)

These bits are used to set the trigger level for the

receive FIFO interrupt.

An interrupt is generated when the number of charac-

ters in the FIFO equals the programmed trigger level.

However the FIFO will continue to be loaded until it is

full.

BIT-7

BIT-6

RX FIFO trigger level

Interrupt Status Register (ISR)

The 554D provides four levels of prioritized interrupts

to minimize external software interaction. The Inter-

rupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the

ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are

acknowledged until the pending interrupt is serviced.

Whenever the interrupt status register is read, the

interrupt status is cleared. However it should be noted

that only the current pending interrupt is cleared by the

read. A lower level interrupt may be seen after reread-

ing the interrupt status bits. The Interrupt Source

Table 7 (below) shows the data values (bit 0-5) for the

four prioritized interrupt levels and the interrupt

sources associated with each of these interrupt levels:

Table 7, INTERRUPT SOURCE TABLE

Priority

[ ISR BITS ]

Level

Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

Source of the interrupt

000110

LSR (Receiver Line Status Register)

000100

RXRDY (Received Data Ready)

001100

RXRDY (Receive Data time out)

000010

TXRDY ( Transmitter Holding Register Empty)

000000

MSR (Modem Status Register)

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