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SLG46108 Datasheet(PDF) 13 Page - Dialog Semiconductor

Part # SLG46108
Description  GreenPAK Ultra-small Programmable Mixed-signal Matrix
PDF  70 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46108 Datasheet(HTML) 13 Page - Dialog Semiconductor

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Page 12 of 69
SLG46108
tpd
Delay
Latch with nRST/nSET (3-bit LUT
shared macrocell inputs)
30.1
34.6
13.2
14.7
9.7
10.6
ns
tpd
Delay
4-bit LUT (shared macrocell inputs)
28.3
25.7
12.3
10.6
9.0
7.7
ns
tpd
Delay
2-bit LUT
17.5
19.4
7.8
8.1
5.9
5.9
ns
tpd
Delay
3-bit LUT
21.7
24.2
9.4
9.8
7.1
7.1
ns
tpd
Delay
CNT/DLY Logic
50.6
42.5
22.0
18.6
15.5
13.3
ns
tpd
Delay
CNT/DLY (shared macrocell inputs)
54.2
46.3
23.4
20.1
16.5
14.3
ns
tpd
Delay
CNT3/DLY3 Rising Edge Detect
(shared macrocell inputs)
108.9
--
49.2
--
34.0
--
ns
tpd
Delay
CNT3/DLY3 Falling Edge Detect
(shared macrocell inputs)
--
108.1
--
48.9
--
33.9
ns
tpd
Delay
CNT3/DLY3 Both Edge Detect (shared
macrocell inputs)
108.4
108.2
49.0
48.9
34.0
33.9
ns
tw
Pulse
Width
CNT3/DLY3 Rising Edge Detect
(shared macrocell inputs)
49.7
--
21.7
--
15.8
--
ns
tw
Pulse
Width
CNT3/DLY3 Falling Edge Detect
(shared macrocell inputs)
--
49.1
--
21.2
--
15.5
ns
tw
Pulse
Width
CNT3/DLY3 Both Edge Detect (shared
macrocell inputs)
47.7
47.1
20.8
20.3
15.2
14.9
ns
tpd
Delay
DFF
29.6
22.1
12.9
9.7
9.5
7.3
ns
tpd
Delay
DFF nReset
--
28.9
--
12.3
--
9.0
ns
tpd
Delay
DFF nSet
--
35.1
--
14.8
--
10.7
ns
tpd
Delay
Filter
183.7
196.7
75.4
78.4
49.5
52.2
ns
tpd
Delay
PDLY 1 Cell Both Edge Delay
352.0
346.5
160.6
157.9
119.2
117.3
ns
tpd
Delay
PDLY 1 Cell Both Edge Detect
39.1
37.7
16.9
16.1
12.2
11.7
ns
tpd
Delay
PDLY 1 Cell Rising Edge Detect
39.1
--
16.9
--
12.2
--
ns
tpd
Delay
PDLY 1 Cell Falling Edge Detect
--
37.7
--
16.1
--
11.7
ns
tpd
Delay
PDLY 2 Cells Both Edge Delay
657.4
653.0
313.2
310.8
224.2
222.5
ns
tpd
Delay
PDLY 2 Cells Both Edge Detect
39.1
37.7
16.9
16.1
12.2
11.7
ns
tpd
Delay
PDLY 2 Cells Rising Edge Detect
39.0
--
16.9
--
12.2
--
ns
tpd
Delay
PDLY 2 Cells Falling Edge Detect
--
37.8
--
16.1
--
11.7
ns
tpd
Delay
PDLY 3 Cells Both Edge Delay
965.1
959.0
460.1
457.0
329.5
324.4
ns
tpd
Delay
PDLY 3 Cells Both Edge Detect
39.1
37.7
16.9
16.1
12.2
11.7
ns
tpd
Delay
PDLY 3 Cells Rising Edge Detect
39.0
--
16.9
--
12.2
--
ns
tpd
Delay
PDLY 3 Cells Falling Edge Detect
--
37.8
--
16.1
--
11.7
ns
tpd
Delay
PDLY 4 Cells Both Edge Delay
1271.5
1266.1
606.9
604.0
434.9
432.8
ns
tpd
Delay
PDLY 4 Cells Both Edge Detect
39.1
37.7
16.9
16.1
12.2
11.7
ns
tpd
Delay
PDLY 4 Cells Rising Edge Detect
39.0
--
16.9
--
12.2
--
ns
tpd
Delay
PDLY 4 Cells Falling Edge Detect
--
37.8
--
16.1
--
11.7
ns
Table 2. Typical Delay estimated for each macrocell
Symbol Parameter
Note
VDD = 1.8 V
VDD = 3.3V
VDD = 5.0V
Unit
rising
falling
rising falling rising falling



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