SLG46400 datasheet(92/95 Pages) DIALOG

92 / 95 page

000-0046400-109

Page 86 of 89

SLG46400

reg<807>

PIN2 edge detect mode

0: Rising edge

1: Falling edge

reg<808>

PIN2 reset Enable

0: Disable

1: Enable

reg<810:809>

Pipe number select from connection matrix out <48>

00: 3 pipes

01: 5 pipes

10: 7 pipes

11: 11 pipes

reg<811>

ACMP0 Low Bandwidth Enable

0: Disable

1: Enable

reg<812>

ACMP1 Low Bandwidth Enable

0: Disable

1: Enable

reg<813>

ADC power down control register when reg<815:814>=”01”. ADC power power is controlled by

reg<813>, otherwise, ADC power down is controlled by connection matrix out<3>.

When reg <814> = “1”:

0: ADC power on

1: ADC power down

<815:814>

ADC/PWM/OSC power down source selection

00: ADC power down from matrix out <3>, PWM power down from register

01: PWM power down from matrix out <3>, ADC power down from reg <813>

10: ADC & PWM power down from matrix out <3>

11: OSC power down from matrix out <3>, PWM & ADC power down from register

reg<816>

Oscillator Dividers control

0:Oscillator Dividers Enabled

1: Oscillator Dividers Diasbled

reg<817>

DFF0/LATCH0 output polarity control

0: Do not invert output polarity

1: Invert output polarity

reg<818>

PWM1 Mode Select

0: Down to 0%

1: Up to 100%

reg<819>

PWM2 Mode Select

0: Down to 0%

1: Up to 100%

reg<821:820>

Pipe number select from connection matrix out <49>

00: 2 pipes

01: 4 pipes

10: 8 pipes

11: 12 pipes

reg<829:822>

8-bit pattern id

reg<830>

NVM data read Disable

0: Disable

1: Enable

reg<831>

NVM power down

0: None

1: Power Down

Bit Address

SLG46400 Datasheet(PDF) 92 Page - Dialog Semiconductor

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