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SLG46534 Datasheet(PDF) 13 Page - Dialog Semiconductor |
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SLG46534 Datasheet(HTML) 13 Page - Dialog Semiconductor |
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13 / 172 page  SLG46534_DS_107 Page 12 of 171 SLG46534 5.8 Timing Estimator 5.9 Typical Counter/Delay Offset Measurements Table 2. Typical Delay Estimated for Each Macrocell at T=25°C Symbol Parameter Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit rising falling rising falling rising falling tpd Delay Digital Input to PP 1X 45 50 19 21 14 15 ns tpd Delay Digital Input with Schmitt Trigger to PP 1X 44 49 19 21 14 15 ns tpd Delay Low Voltage Digital input to PP 1X 46 447 19 195 14 134 ns tpd Delay Digital input to PMOS output 44 - 19 - 14 - ns tpd Delay Digital input to NMOS output - 81 - 30 - 20 ns tpd Delay Output enable from pin, OE Hi-Z to 1 48 - 20 - 15 - ns tpd Delay Output enable from pin, OE Hi-Z to 0 - 46 - 20 - 24 ns tpd Delay LUT2bit (LATCH) 34 33 14 13 10 9 ns tpd Delay LATCH (LUT2bit) 30 34 14 13 10 9 ns tpd Delay LUT3bit (LATCH) 383718151310 ns tpd Delay LATCH+nRESET (LUT3bit) 45 42 21 17 15 12 ns tpd Delay LATCH 33 5 14 14 ns tpd Delay LUT4bit 28 33 14 13 10 9 ns tpd Delay LUT2bit 31 31 14 13 10 9 ns tpd Delay LUT3bit 35 33 15 13 11 10 ns tpd Delay CNT/DLY Logic 626827291920 ns tpd Delay DFF 32281412 11 9 ns tpd Delay P_DLY1C 626827291920 ns tpd Delay P_DLY2C 667 656 303 297 225 221 ns tpd Delay P_DLY3C 968 956 440 434 327 322 ns tpd Delay P_DLY4C 1265 1252 576 570 428 423 ns tpd Delay Filter 213 210 84 83 55 55 ns tpd Delay ACMP (5 mV overdrive, IN- = 600 mV) 1600 1900 1500 1800 1600 1800 ns tw width I/O with 1X push pull (min transmitted) 20 20 20 20 20 20 ns tw width filter (min transmitted) 150 150 55 55 35 35 ns Table 3. Typical Counter/Delay Offset Measurements Parameter RC OSC Freq RC OSC Power VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit Offset (Power On Delay) 25 kHz auto 1.6 1.6 1.6 s Offset (Power On Delay), fast start 25 kHz auto 2.1 2.1 2.1 s Offset (Power On Delay) 2 MHz auto 0.4 0.2 0.2 s Offset (Power On Delay), fast start 2 MHz auto 0.7 0.5 0.4 s Offset (Power On Delay) 25 MHz auto 0.01 0.05 0.04 s Frequency settling time 25 kHz auto 19 14 12 s Frequency settling time 2 MHz auto 14 14 14 s Variable (CLK period) 25 kHz forced 0-40 0-40 0-40 s Variable (CLK period) 2 MHz forced 0-0.5 0-0.5 0-0.5 s Variable (CLK period) 25 MHz 0-0.04 0-0.04 0-0.04 s |
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