Symbol

Parameter

Conditions

Min

Typ

Max

Units

Clock Input Frequency

(Notes 3 4)

800

kHz

Clock Input High Time

300

ns

Clock Input Low Time

300

ns

Data Input Setup Time

100

ns

Data Input Hold Time

100

ns

Enable Input Setup Time

100

ns

Enable Input Hold Time

100

ns

Data Output Clock Low to

500

ns

Data Out Time

Note 2

Note that for timing purposes the signals ENABLE and BLANK can be considered to be totally independent of each other

Note 3

Note 4

Clock input rise and fall times must not exceed 5 ms

Connection Diagrams

Dual-In-Line Package

TLF5603 – 2

Top View

Order Number MM58341N

See NS Package Number N40A

Plastic Chip Carrier

TLF5603 – 8

Top View

Order Number MM58341V

See NS Package Number V44A

Functional Description

This product is specifically designed to drive multiplexed or

non-multiplexed high voltage alphanumeric or dot matrix

vacuum fluorescent (VF) displays Character generation is

done externally in the microprocessor with a serial data

path to the display driver The MM58341 uses three signals

DATA IN CLOCK and ENABLE where ENABLE acts as an

external load signal Display blanking can be achieved by

means of the BLANKING CONTROL input and a logic ‘1’

will turn off all sections of the display A block diagram of

the MM58341 is shown in

Figure 1

Figure 2 shows the pinout of the MM58341 device where

output 1 (pin 18) is equivalent to bit 1 (ie the first bit of data

to be loaded into the shift register following ENABLE high)

A logic ‘1’ at the input will turn on the corresponding display

digitsegmentdot output

A significant reduction in discrete board components can be

achieved by use of the MM58341 because external pull-

down resistors are not required Due to the nature of the

output stage both its on and off impedance values vary as a

function of the display voltage applied However

Figures 3a

and

3b show that this output impedance will remain con-

stant for a fixed value of display voltage

Figure 4 demonstrates the critical timing requirements be-

tween CLOCK and DATA IN for the MM58341

To clear (reset) the display driver at power on or any time

the following flushing routine may be used With the enable

signal high clock in 32 zeroes Drive the enable signal low

and the display will be blank It is recommended to clear the

driver at power on

In

Figure 5 the ENABLE signal acts as an envelope and

only while this signal is at a logic ‘1’ does the circuit accept

CLOCK input signals Data is transferred and shifted in the

internal shift register on the rising clock edge ie

‘0’ – ‘1’

transition When the ENABLE signal goes low the contents

of the shift registers are latched and the display will show

new data During data transfer the display will show old

data DATA OUT is also provided on the MM58341 being

output on the falling edge At any time the display may be

blanked under processor control using the BLANKING

CONTROL input

Figure 6 shows a schematic diagram of a microprocessor-

based system where the MM58341 is used to provide the

grid drive for a 32-digit5x7dot matrix vacuum fluorescent

(VF) display The anode drive in this example is provided by

another member of the high voltage display driver family

namely the MM58348 which does not require an externally

generated load signal

3