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HT67F5650 Datasheet(PDF) 21 Page - Holtek Semiconductor Inc

Part # HT67F5650
Description  24-Bit Delta Sigma A/D LCD Flash MCU
PDF  235 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT67F5650 Datasheet(HTML) 21 Page - Holtek Semiconductor Inc

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Rev. 1.30
�0
De�e��e� 1�� �01�
Rev. 1.30
�1
De�e��e� 1�� �01�
HT67F5650/HT67F5660
24-Bit Delta Sigma A/D + LCD Flash MCU
HT67F5650/HT67F5660
24-Bit Delta Sigma A/D + LCD Flash MCU
Symbol
Parameter
Test Conditions
Min.
Typ. Max. Unit
VDD
Conditions
Stand�y Cu��ent (Sleep0)
(HXT� fSYS=off� fS=fSUB=fLXT o� fLIRC)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT disa�le� fSYS=1�MHz
─
0.�
0.8
μA
5V
─
0.5
1.0
μA
Stand�y Cu��ent (Sleep0)
(LXT� fSYS=off� fS=fSUB=fLXT)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT disa�le�
fSYS=3�7�8Hz
─
0.�
0.8
μA
5V
─
0.5
1.0
μA
Stand�y Cu��ent (Sleep1)
(HXT� fSYS=off� fS=fSUB=fLXT)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT ena�le� fSYS=1�MHz
─
1.3
5
μA
5V
─
�.�
10
μA
Stand�y Cu��ent (Sleep1)
(HXT� fSYS=off� fS=fSUB=fLIRC)
3V No load� syste� HALT� LDO� ADC
off� WDT ena�le� fSYS=1�MHz
─
1.3
5
μA
5V
─
�.�
10
μA
Stand�y Cu��ent (Sleep1)
(LXT� fSYS=off� fS=fSUB=fLXT)
3V No load� syste� HALT� LDO� ADC
off� WDT ena�le� fSYS=3�7�8Hz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Sleep1)
(HXT� fSYS=off� fS=fSUB=fLXT o� fLIRC)
─
No load� syste� HALT� LDO� LCD�
ADC off� WDT disa�le� fSYS=1�MHz�
LVR ena�le and LVDEN=1
─
90
1�0
μA
Stand�y Cu��ent (Idle0)
(HXT� fSYS=off� fS=T1)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT ena�le� fSYS=1�MHz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle0)
(HXT� fSYS=off� fS=fSUB=fLXT o� fLIRC)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT ena�le� fSYS=1�MHz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle0)
(HIRC� fSYS=off� fS=fSUB=fLIRC)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=�.915�×3MHz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle0)
(HXT� fSYS=off� fS=fSUB=fLXT o� fLIRC)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=1�MHz/��
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle0)
(LXT� fSYS=off� fS=T1)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=3�7�8Hz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle0)
(LXT� fSYS=off� fS=fSUB=fLXT)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=3�7�8Hz
─
1.3
3.0
μA
5V
─
�..�
5.0
μA
Stand�y Cu��ent (Idle0)
(LIRC� fSYS=off� fS=fSUB=fLIRC)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT ena�le� fSYS=3�kHz
─
1.3
3.0
μA
5V
─
�.�
5.0
μA
Stand�y Cu��ent (Idle1)
(LXT� fSYS=fSUB=fLXT� fS=fSUB=fLXT)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=3�7�8Hz
─
1.9
�.0
μA
5V
─
3.3
7.0
μA
Stand�y Cu��ent (Idle1)
(HXT� fSYS=fL� fS=fSUB=fLXT o� fLIRC)
3V No load� syste� HALT� LDO�
LCD� ADC off� WDT ena�le�
fSYS=1�MHz/��
─
0.3�
0.�
�A
5V
─
0.85
1.�
�A
Stand�y Cu��ent (Idle1)
(HXT� fSYS=fH� fS=fSUB=fLXT o� fLIRC)
3V No load� syste� HALT� LDO� LCD�
ADC off� WDT ena�le� fSYS=1�MHz
─
0.�
1.0
�A
5V
─
1.�
�.0
�A
VIL
Input Low Voltage fo� I/O Po�ts�
TCK� TP� INT0 and INT1
—
—
0
—
0.�VDD V
5V
—
0
—
1.5
V
VIH
Input High Voltage fo� I/O Po�ts�
TCK� TP� INT0 and INT1
—
—
0.8VDD
—
VDD
V
5V
—
3.5
—
5
V
VLVR
Low Voltage Reset Voltage
—
LVR ena�le� �.10V option
-5%
�.1
+5%
V
LVR ena�le� �.55V option
�.55
V
LVR ena�le� 3.15V option
3.15
V
LVR ena�le� 3.80V option
3.8
V
ILVR
Low Voltage Reset Cu��ent
— LVR ena�le� LVDEN=0
—
�0
90
μA



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