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74LVC38AD Datasheet(PDF) 5 Page - NXP Semiconductors

Part # 74LVC38AD
Description  Quad 2-input NAND gate (open drain)
PDF  14 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC38AD Datasheet(HTML) 5 Page - NXP Semiconductors

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2004 Mar 22
5
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
Fig.5 Logic diagram (one gate).
handbook, halfpage
MNA699
Y
GND
A
B
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70
°C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C derate linearly with 4.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
for maximum speed performance
2.7
3.6
V
for low-voltage applications
1.2
3.6
V
VI
input voltage
0
5.5
V
VO
output voltage
0
5.5
V
Tamb
operating ambient temperature
−40
+125
°C
tr,tf
input rise and fall times
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−0.5
+6.5
V
IIK
input diode current
VI <0
−−50
mA
VI
input voltage
note 1
−0.5
+6.5
V
IOK
output diode current
VO <0
−−50
mA
VO
output voltage
note 1
−0.5
+6.5
V
IO
output sink current
VO =0toVCC
−
50
mA
ICC, IGND
VCC or GND current
−±100
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation
Tamb = −40 to +125 °C; note 2
−
500
mW



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