CYRF8935 datasheet(23/40 Pages) CYPRESS

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CYRF8935

Document Number: 001-61351 Rev. *K

Page 23 of 40

Table 11. Framer Register Information

Bit No.

Bit Name

R/W

Description

Default

15:13

PREAMBLE_LEN

R/W

000b: 1 byte

001b: 2 bytes

010b: 3 bytes

111b: 8 bytes

010b

12:11

SYNCWORD_LEN

R/W

11b: 64 bits

{{Reg39[15:0],Reg38[15:0],Reg37[15:0],Reg36[15:0]}

10b: 48 bits, {Reg39[15:0],Reg38[15:0],Reg36[15:0]}

01b: 32 bits, {Reg39[15:0],Reg36[15:0]

00b: 16 bits,{Reg36[15:0]}

11b

10:8

TRAILER_LEN

R/W

000b: 4 bits

001b: 6 bits

010b: 8 bits

011b: 10 bits

111b: 18 bits

000b

7:6

DATA_PACKET_TYPE

R/W

00b: Non return to zero (NRZ) law data

00b

5:4

FEC_TYPE

R/W

00b: No FEC

01b: Reserved

10b: FEC23

11b: Reserved

00b

3:1

BRCLK_SEL

R/W

Selects output clock signal to BRCLK[7] pin:

000b: Keep low

001b: Crystal buffer out

010b: Crystal divided by 2

011b: Crystal divided by 4

100b: Crystal divided by 12

101b: TXCLK 1 MHz

110b: APLL_CLK (12 MHz during Tx, Rx)

111b: Keep low

011b

(Reserved)

W/R

(Reserved)

SLEEP_MODE

1: Enter SLEEP state (set crystal gain block to off. Keep LDO

regulator on (register values will be preserved).

Wakeup begins when SPI_SS goes low. This restarts the on-chip

clock oscillator to begin normal operation.

0: Normal (IDLE) state

(Reserved)

BRCLK_ON_SLEEP

R/W

1: Crystal running at sleep mode

Draws more current but enables fast wakeup

0: Crystal stops during sleep mode

Saves current but takes longer to wake up

Note

7. BRCLK signal is available on bare die only, not packaged parts.

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