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LANSDALE Semiconductor, Inc.

ML145106

TYPICAL CHARACTERISTICS*

* Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance.

OSCin, MAXIMUM FREQUENCY (MHz)

fin, MAXIMUM FREQUENCY (MHz)

50

40

30

20

10

0

0

5.0

10

15

20

25

+ 85°C

– 40°C

+ 25°C

50

40

30

20

10

0

0

5.0

10

15

20

25

+ 85°C

– 40°C

+ 25°C

Figure 1. Maximum Divider Input Frequency

versus Supply Voltage

Figure 2. Maximum Oscillator Input Frequency

versus Supply Voltage

PIN DESCRIPTIONS

P0 – P8

Programmable Inputs (PDIP – Pins 17 – 9; SOG – Pins 19,

17 – 14, 12 – 9)

Programmable divider inputs (binary).

fin

Frequency Input (PDIP, SOG – Pin 2)

Frequency input to programmable divider (derived

fromVCO).

OSCin, OSCout

Oscillator Input and Oscillator Output (PDIP, SOG –

Pins 3, 4)

Oscillator/amplifier input and output terminals.

LD

Lock Detector (PDIP, SOG – Pin 8)

LD is high when loop is locked, pulses low when

out–of–lock.

φDetout (PDIP, SOG – Pin 7)

Signal for control of external VCO, output high when fin/N

is less than the reference frequency; output low when fin/N is

greater than the reference frequency. Reference frequency is

the divided down oscillator–input frequency typically 5.0 or 10

kHz.

NOTE

Phase Detector Gain = VDD/4

π.

FS

Reference Oscillator Frequency Division Select (PDIP,SOG

– Pin 6)

When using 10.24 MHz OSC frequency, this control selects

10 kHz, a “0” selects 5.0 kHz.

÷2out (PDIP, SOG – Pin 5)

Reference OSC frequency divided by 2 output; when using

10.24 MHz OSC frequency, this output is 5.12 MHz for fre-

quency tripling applications.

VDD

Positive Power Supply (PDIP, SOG – Pin 1)

VSS

Ground (PDIP – Pin 18, SOG – Pin 20)

TRUTH TABLE

Selection

P8

P7

P6

P5

P4

P3

P2

P1

P0

Divide by N

0

0

0

0

0

0

0

0

0

2*

0

0

0

0

0

0

0

0

1

3*

0

0

0

0

0

0

0

1

0

2

0

0

0

0

0

0

0

1

1

3

0

0

0

0

0

0

1

0

0

•••••••••

4

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

0

1

1

1

1

1

1

1

1

255

1

1

1

1

1

1

1

1

1

511

1: Voltage level = VDD.

0: Voltage level = 0 or open circuit input.

* The binary setting of 00000000 and 00000001 on P8 to P0 results

in a 2 and 3 division which is not in the 2N – 1 sequence. When pin

is not connected the logic signal on that pin can be treated as a “0”.