4100 datasheet(4/43 Pages) CYPRESS

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Document Number: 001-87220 Rev. *J

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PSoC® 4: PSoC 4100 Family

Datasheet

Figure 2. Block Diagram

The PSoC 4100 devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The ARM Serial_Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator Integrated Development Environment (IDE)

provides fully integrated programming and debug support for the

PSoC 4100 devices. The SWD interface is fully compatible with

industry standard third party tools. With the ability to disable

debug features, with very robust flash protection, and by allowing

customer-proprietary functionality to be implemented in on-chip

programmable blocks, the PSoC 4100 family provides a level of

security not possible with multi-chip application solutions or with

microcontrollers.

The debug circuits are enabled by default and can only be

disabled in firmware. If not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. Because all programming, debug, and test inter-

faces are disabled when maximum device security is enabled,

PSoC 4100 with device security enabled may not be returned for

failure analysis. This is a trade-off the PSoC 4100 allows the

customer to make.

PSoC 4100

32-bit

AHB-Lite

CPU Subsystem

SRAM

Up to 4 kB

SRAM Controller

ROM

4 kB

ROM Controller

FLASH

Up to 32 kB

Read Accelerator

Deep Sleep

Hibernate

Active/Sleep

SW D

NVIC, IRQM X

Cortex

24 M Hz

FAST M UL

System Interconnect (Single Layer AHB)

IO Subsystem

36x GPIOs

Peripherals

System Resources

Power

Clock

WDT

ILO

Reset

Clock Control

DFT Logic

Test

IM O

DFT Analog

Sleep Control

PW RSYS

REF

POR

LVD

NVLatches

BOD

WIC

Reset Control

XRES

Peripheral Interconnect (M M IO)

PCLK

Port Interface & Digital System Interconnect (DSI)

Power M odes

CTBm

SMX

SAR ADC

(12-bit)

Program m able

Analog

2x OpAm p

High Speed I/O M atrix

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