MB9B210T datasheet(2/141 Pages) CYPRESS

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MB9B210T Series

32-bit Arm® Cortex®-M3

FM3 Microcontroller

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 002-04680 Rev. *D

Revised January 15, 2018

The MB9B210T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance

and competitive cost.

These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions

such as Motor Control Timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C, LIN, Ethernet-MAC). The products

which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family PERIPHERAL MANUAL".

Features

32-bit Arm Cortex-M3 Core

Processor version: r2p1

Up to 144 MHz Frequency Operation

Memory Protection Unit (MPU): improves the reliability of an

embedded system

Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

24-bit System timer (Sys Tick): System timer for OS task

management

On-chip Memories

[Flash memory]

Up to 1 Mbyte

Built-in Flash Accelerator System with 16 Kbyte trace buffer

memory

The read access to Flash memory can be achieved without

wait cycle up to operation frequency of 72 MHz. Even at the

operation frequency more than 72 MHz, an equivalent

access to Flash memory can be obtained by Flash

Accelerator System.

Security function for code protection

[SRAM]

This Series contain a total of up to 128 Kbyte on-chip SRAM.

This is composed of two independent SRAM (SRAM0,

SRAM1) . SRAM0 is connected to I-code bus and D-code

bus of Cortex-M3 core. SRAM1 is connected to System bus.

SRAM0: Up to 64 Kbyte.

SRAM1: Up to 64 Kbyte.

External Bus Interface

Supports SRAM, NOR and NAND Flash device

Up to 8 chip selects

8-/16-bit Data width

Up to 25-bit Address bit

Maximum area size: Up to 256 Mbytes

Supports Address/Data multiplex

Supports external RDY input

USB Interface (Max 2 channels)

USB interface is composed of Device and Host.

PLL for USB is built-in, USB clock or Ethernet clock can be

generated by multiplication of Main clock.

[USB device]

USB2.0 Full-Speed supported

Max 6 EndPoint supported



EndPoint 0 is control transfer



EndPoint 1, 2 can be selected Bulk-transfer,

Interrupt-transfer or Isochronous-transfer



EndPoint 3-5 can be selected Bulk-transfer or

Interrupt-transfer



EndPoint 1 to 5 is comprised Double Buffer

• EndPoint 0, 2 to 5:64 bytes

• EndPoint 1: 256 bytes

[USB host]

USB2.0 Full/Low speed supported

Bulk-transfer, interrupt-transfer and Isochronous-transfer

support

USB Device connected/dis-connected automatically detect

IN/OUT token handshake packet automatically

Max 256-byte packet-length supported

Wake-up function supported

Ethernet-MAC (Max 1 channel)

Compliant with IEEE802.3 specification

10Mbps / 100 Mbps data transfer rates supported

MII/RMII for external PHY device supported.



MII: Max 1channel



RMII: Max 1channel

Full-Duplex and Half-Duplex mode supported.

Wake-ON-LAN supported

Built-in dedicated descriptor-system DMAC

Built-in 2 Kbyte Transmit FIFO and 2 Kbyte Receive FIFO.

Compliant IEEE1558-2008 (PTP)

MB9B210T Datasheet(PDF) 2 Page - Cypress Semiconductor

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