38C1 datasheet(21/59 Pages) MITSUBISHI

21 / 59 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

38C1 Group

TIMERS

The 38C1 group has five timers: timer X, timer Y, timer 1, timer 2,

and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,

timer 2, and timer 3 are 8-bit timers.

All timers are down count timers. When the timer reaches “0”, an

underflow occurs at the next count pulse and the corresponding

timer latch is reloaded into the timer and the count is continued.

When a timer underflows, the interrupt request bit corresponding

to that timer is set to “1”.

Read and write operation on 16-bit timer must be performed for

both high- and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write the

low-order byte first. The 16-bit timer cannot perform the correct

operation when reading during the write operation, or when writing

during the read operation.

Fig. 18 Timer block diagram

"1"

P53/CNTR1

"0"

"10"

"00","01","11"

P52/CNTR0

P52 direction register

Pulse output mode

P52 latch

"0"

"1"

"0"

"1"

"10"

Pulse width

measurement mode

CNTR0 edge switch bit

"0"

P62 direction register

P62 latch

"0"

"1"

TOUT output

edge switch bit

"0"

"1"

TOUT output

control bit

"1"

P62/TOUT

f(XCIN)

"0"

"1"

TOUT output control bit

φSOURCE/16

"11"

φSOURCE/16

"1"

"0"

Count source selection bit (Note 1)

φSOURCE

φSOURCE/16

f(XIN)/16

(Note 2)

Timer 1 count source

selection bit (Note 1)

CNTR1 active

edge switch bit

Timer Y stop

control bit

Falling edge detection

Period

measurement mode

Timer Y

interrupt

request

Pulse width HL continuously

measurement mode

Rising edge detection

Timer Y

operating

mode bits

(Note 1)

Timer X

interrupt

request

Pulse output mode

Timer X stop

control bit

Timer X write

control bit

Timer X operat-

ing mode bits

“00”,“01”,“11”

CNTR0 active

edge switch bit

Timer 2 write

control bit

Timer 3 count

source selection bit

(Note 1)

Timer 2

interrupt

request

Timer 3

interrupt

request

Timer 2 count source

selection bit

(Note 1)

Timer 1

interrupt

request

Data bus

Timer Y (low) (8)

Timer Y (high) (8)

Timer 3 latch (8)

Timer 3 (8)

Timer 1 latch (8)

Timer 1 (8)

Timer 2 latch (8)

Timer 2 (8)

Timer X (low) (8)

Timer X (high) (8)

Timer X (low) latch (8) Timer X (high) latch (8)

Timer Y (low) latch (8)Timer Y (high) latch (8)

Timer Y operating mode bits

“00”,“01”,“10”

CNTR0

interrupt

request

CNTR1

interrupt

request

φSOURCE: represents the supply source of internal clock φ. It is the oscillation frequency of XIN input

in the middle- and high-speed mode, built-in ring oscillator in the ring oscillator mode,

and sub-clock in the low-speed mode.

Notes 1: Internal clock in the low-speed mode is the sub-clock oscillation/2.

Internal clock in the ring oscillator mode is the internal ring oscillator oscillation/8.

Except CNTR input, timer 1 and timer 3 count sources, the clock except system clock cannot

be used as the count source.

φSOURCE can be selected as the timer X count source only in the pulse output mode.

Write “0” to the count source selection bit except in the pulse output mode.

38C1 Datasheet(PDF) 21 Page - Mitsubishi Electric Semiconductor

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