AC101L-DS05-R datasheet(43/54 Pages) BOARDCOM

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Preliminary Data Sheet

AC101L

8/9/04

B roa dcom Co rpo rat ion

Document

AC101L-DS06-R

10BASE-T MII Transmit System Timing

Page 33

10BASE-T MII TRANSMIT SYSTEM TIMING

Figure 7: 10BASE-T Transmit Timing

Table 40: 10BASE-T MII Transmit System Timing

Parameter

SYM

Conditions

Min

Typ

Max

Units

TX_CLK period

tCK

–

399.98

400.00

400.02

TX_CLK high period

tCKH

–

180.00

200.00

220.00

TX_CLK low period

tCKL

–

180.00

200.00

220.00

TXEN to SOP

tTJ

–

240

–

360

TXEN sampled to CRS

tTCSA

RPTR is logic low

–

130

TXEN sampled to COL

tTCLA

RPTR is logic low

–

300

!TXEN to EOP

tTJ

–

240

–

360

!TXEN sampled to !CRS

tTCSD

RPTR is logic low

–

130

!TXEN sampled to !COL

tTCLD

RPTR is logic low

–

300

TX propagation delay

tTJ

From TXD[3:0] to TXOP/N

240

–

360

TXD[3:0], TXEN, TXER setup

tTXS

From rising edge of TX_CLK

–

TXD[3:0], TXEN, TXER hold

tTXH

From rising edge of TX_CLK

–

tTX_T

CRS

TX_CLK

TXEN

TXD[3:0]

TX_ER

TXOP/N

COL

tCK

tCKH

tCKL

tTXS

tTXH

tTCS

tTCLA

tTCLD

Start of

Packet

End of

Packet

tTJ

tTX_TX

tTCSD

tTCSA

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