HT16515 datasheet(5/12 Pages) HOLTEK

5 / 12 page

A.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDD

Conditions

tPHL

Logic Supply Voltage

CLK

®DO

CL=15pF, RL=10k

¾¾

300

tPLH

¾¾

300

tr1

Rise Time

CL=300pF, S1~S16

¾¾

tr2

CL=300pF, G1~G4

S17/G12~S24/G5

¾¾

0.5

Fall Time

CL=300pF, Sn, Gn

¾¾

120

tmax

Maximum Clock Frequency

Duty=50%

¾¾

MHz

Input Capacitance

¾¾

tCW

Clock Pulse Width

400

¾¾

tSW

Strobe Pulse Width

¾¾

tSU

Data Setup Time

100

¾¾

Data Hold Time

100

¾¾

tCS

Clock-Strobe Time

CLK rising edge to CS rising edge

¾¾

Wait Time

CLK rising edge to CLK falling edge

¾¾

HT16515

Rev. 1.00

December 19, 2003

Functional Description

Display RAM and Display Mode

The static display RAM stores the data transmitted from

an external device to the HT16515 through a serial inter-

face. The contents of the RAM are directly mapped to

the contents of the VFD driver. Data in the RAM can be

accessed through the data setting, address setting and

display control commands. It is assigned as addresses

in 8-bit unit as follows:

Dimming Control

HT16515 provides an 8-step dimmer function on display

by controlling the 3-bit binary command code. The full

pulse width of grid signal is divided into 16 uniform sec-

tions by PWM (pulse width modulation) technology.

The 16 uniform sections available form an 8-step dim-

mer via 3-bit binary code. The 8-step dimmer includes

1/16, 2/16, 4/16, 10/16, 11/16, 12/16, 13/16 and 14/16.

The 1/16 pulse width indicates minimum lightness. The

14/16 pulse width represents maximum lightness (Refer

to the display control command).

Key Matrix and Key-Input Data Storage RAM

The key matrix scans the series key states at each level

of the key strobe signal (Seg1/K1~Seg16/K16) output of

the HT16515. The key strobe signal outputs are

time-multiplexed signals from Seg1/K1~Seg16/K16.

The states of inputs K0 and K1 are sampled by strobe

signal Seg1/K1~Seg16/K16 and latched into the regis-

ter.

0 1 H U

0 4 H U

0 7 H U

0 A H U

0 D H U

1 0 H U

1 3 H U

1 6 H U

1 9 H U

1 C H U

1 F H U

2 2 H U

0 0 H L

0 3 H L

0 6 H L

0 9 H L

0 C H L

0 F H L

1 2 H L

1 5 H L

1 8 H L

1 B H L

1 E H L

2 1 H L

0 0 H U

0 3 H U

0 6 H U

0 9 H U

0 C H U

0 F H U

1 2 H U

1 5 H U

1 8 H U

1 B H U

1 E H U

2 1 H U

S E G 1

S E G 4

S E G 8

S E G 1 2

S E G 1 6

S E G 2 0

0 1 H L

0 4 H L

0 7 H L

0 A H L

0 D H L

1 0 H L

1 3 H L

1 6 H L

1 9 H L

1 C H L

1 F H L

2 2 H L

0 2 H L

0 5 H L

0 8 H L

0 B H L

0 E H L

1 1 H L

1 4 H L

1 7 H L

1 A H L

1 D H L

2 0 H L

2 3 H L

D I G 1

D I G 2

D I G 3

D I G 4

D I G 5

D I G 6

D I G 7

D I G 8

D I G 9

D I G 1 0

D I G 1 1

D I G 1 2

X X H L

X X H U

b 0

b 3 b 4

b 7

L o w e r

4 b i t s

H i g h e r

4 b i t s

0 2 H U

0 5 H U

0 8 H U

0 B H U

0 E H U

1 1 H U

1 4 H U

1 7 H U

1 A H U

1 D H U

2 0 H U

2 3 H U

S E G 2 4

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