M74HC279

2/10

IINPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

NOTE : Q0 = The level of Q before the indicated input condition was

established.

# : For latches with double S input :

H : Both S inputs high

L : One of both inputs low

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

1, 5, 10, 14

1R to 4R

Reset Inputs (Active Low)

2, 3, 6, 11,

12, 15

1S1, 1S2,

2S, 3S1,

3S2, 4S

Set Inputs (Active Low)

4, 7, 9, 13

1Q to 4Q

Outputs

8

GND

Ground (0V)

16

Positive Supply Voltage

S #R

Q

HH

Q0

LH

H

HL

L

LL

H