SIP12110DB datasheet(4/16 Pages) VISHAY

4 / 16 page

SiP12110

www.vishay.com

Vishay Siliconix

S14-1891-Rev. A, 15-Sep-14

Document Number: 64299

For technical questions, contact: powerictechsupport@vishay.com

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FUNCTIONAL BLOCK DIAGRAM

Fig. 2 - SiP12110 Functional Block Diagram

PIN CONFIGURATION

Fig. 3 - SiP12110 Pin Configuration (Top View)

PIN CONFIGURATION

PIN NUMBER

NAME

FUNCTION

1, 16

VIN

Input supply voltage for power MOS. VIN = 4.5 V to 15 V

2VCC

Internal regulator output, tie VCC to VIN when VIN < 5.5 V

3AGND

Analog ground

4RON

An external resistor between RON and AGND sets the switching on time.

COMP

Connect to an external RC network for loop compensation and droop function.

6VFB

Feedback voltage. 0.6 V (typ.). Use a resistor divider between VOUT and AGND to set the output voltage.

An external capacitor between SS and AGND sets the soft start time.

Enable pin. Pull enable above 1.5 V to enable and below 0.4 V to disable the part. Do not float this pin.

9PGOOD

Power good output. Open drain.

10, 11, 12

Switching node, inductor connection point

BOOT

Bootstrap pin - connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply

for the high-side gate drive.

14, 15, PAD

PGND

Power ground

On-time

generator

PWM

comparator

Soft

start

0.6 V

reference

AGND

PGOOD

VCC

VFB

VIN

PGND

VIN

VCC

Anti-

XCOND

control

ZCD

0.72 V

OV comparator

Control

logic

sectionl

OCP

UVLO

OTP

COMP

OTA

Isense

I-V

converter

Isense

RON

0.45 V

VFB

UV comparator

Current

mirror

5 V

regulator

VCC

5 μA

VCC

PGND

BOOT

PAD

PGOOD

PGND

AGND

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