LM12434CIWM datasheet(39/80 Pages) NSC

39 / 80 page

60 Operational Information (Continued)

63 INSTRUCTION SEQUENCER

The Sequencer uses a 3-bit counter (Instruction Pointer or

IP) to retrieve the programmable conversion instructions

stored in the Instruction RAM The counter is reset to 000

during chip reset or if the current executed instruction has

its Loop bit (Bit 1 in any Instruction RAM ‘‘00’’) set high

(‘‘1’’) It increments at the end of the currently executed

instruction and points to the next instruction It will continue

to increment up to 111 unless an instruction’s Loop bit is

set If this bit is set the counter resets to ‘‘000’’ and execu-

tion begins again with the first instruction If all instructions

have their Loop bit reset to ‘‘0’’ the Sequencer will execute

all eight instructions continuously Therefore it is important

to realize that if less than eight instructions are pro-

grammed the Loop bit on the last instruction must be set

Leaving this bit reset to ‘‘0’’ allows the Sequencer to exe-

cute ‘‘unprogrammed’’ instructions the results of which may

be unpredictable

The Sequencer’s Instruction Pointer value is readable at

any time and is found in the Status register at Bits 8 – 10

Figure 10 illustrates the instruction execution flow as per-

formed by the sequencer The Sequencer can go through

eight states during instruction execution

State 0

The current instruction’s first 16 bits are read

from the Instruction RAM ‘‘00’’ This state is one clock cycle

long

State 1

Checks the state of the Calibration and Start bits

This is the ‘‘rest’’ state whenever the Sequencer is stopped

using the reset a Pause command or the Start bit is reset

low (‘‘0’’) When the Start bit is set to a ‘‘1’’ this state is one

clock cycle long

State 2

Perform calibration If bit 2 or bit 6 of the Configu-

ration register is set to a ‘‘1’’ state 2 is 76 clock cycles long

If the Configuration register’s bit 3 is set to a ‘‘1’’ state 2 is

4944 clock cycles long

State 3

Run the internal 16-bit Timer The number of

clock cycles for this state varies according to the value

stored in the Timer register The number of clock cycles is

found by using the expression below

32T a 2

where 0 s T s 216 b1

State 7

Sample the input signal and read Limit

1’s val-

ue if needed The number of clock cycles for acquiring the

input signal in the 12-bit a sign mode varies according to

9 a 2D

where D is the user-programmable 4-bit value stored in bits

12 – 15 of Instruction RAM ‘‘00’’ and is limited to 0 s D s

The number of clock cycles for acquiring the input signal in

the 8-bit a sign or ‘‘watchdog’’ mode varies according to

2 a 2D

State 6

Perform first watchdog comparison This state is

5 clock cycles long

State 4

Read Limit

2 This state is 1 clock cycle long

State 5

Perform a conversion or second watchdog com-

parison This state takes 44 clock cycles for a 12-bit a sign

conversions or 21 clock cycles for a 8-bit a sign conver-

sions The ‘‘watchdog’’ comparison mode takes 5 clock cy-

cles

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