CTS9513API-2 datasheet(4/28 Pages) ETC

4 / 28 page

Celeritous Technical Services Corp

800.687.6510 / 806.793.0708

3308 34th St

FAX

806.793.0710

Lubbock, Texas 79410

http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

On power-up, the data bus is configured for 8

bit transfers. The data bus may be reconfig-

ured for 16 bit by programming Master Mode

should be pulled up.

!CS (Chip Select Input)

The chip select line is an active low I/O control

signal used to enable the device for read and

write operations.

!WR (Write Input)

The write line is an active low I/O control

signal which is used to transfer information

from the data bus to one of the internal

command or data registers.

!RD (Read Input)

The read line is an active low I/O control

signal which is used to transfer information

from one of the internal data or command

registers to the data bus.

C/!D (Control/Data Port Select Input)

The C/D line is used in conjunction with the

CS, RD, and WR to select which internal

command or data register is being written to

or read from. The C/D line selects between

the command and data register sets as

summarized in Table 3

FUNCTIONAL DESCRIPTION

SYSTEM LEVEL

The CTS9513 is addressed by the external system

through two address locations. Counter and com-

mand data are written to individual counters through

a sequence of indirectly addressing the internal com-

mand or data register through the command port

address, followed by a write to the data port address

which points to the indirectly addressed register

location.

Data is transferred through either two 8 bit transfers

or a single 16 bit transfer. Pointer sequencing for 8 bit

transfers is automatic and is transferred as least

significant byte first, most significant byte second.

Rapid

programming

the

CTS9513

may

accomplished by use of the auto-increment feature of

the data pointer. This feature is enabled by setting

Master Mode Register bit 14 (MM14). When enabled,

the data pointer may be sequenced through a single

counter group, all counter group registers, all counter

group Hold registers only, or just the control group

registers.

INTERNAL CONFIGURATION

Overview

A simplified block diagram of the CTS9513 is shown

in Figure 4. This diagram shows the major device

elements consisting of:

•

five counter groups,

•

internal frequency prescaler which divides

down the primary external clock source from

clock input X2,

•

external

FOUT

clock

prescalers

which

provide prescaled or divided outputs from a

variety of sources,

•

the Bus interface,

•

Master mode register and

•

the status register.

Not shown are the extended set registers, power-on

reset circuitry or internal control lines. The counter

group block diagrams are shown in Figures 5 and 6.

Counter groups 1 and 2 as shown in Figure 5 have

an additional programmable alarm register and 16 bit

comparator for implementation of time-of-day and

alarm functions.

Counter Groups

All of the counter groups have a 16 bit counter and

four

programmable

registers.

The

primary

and

auxiliary counter mode register controls the count

source, gating and counting modes, input and output

polarities,

binary

BCD

counting

and

other

parameters.

Load Register

The Load register is the primary register used for

storing count-up or count-down values which may be

automatically reloaded into the counter for repetitive

counting.

Hold Register

The Hold register may be used for storing the

instantaneous count value without disturbing the

count process for reading by the host system. It may

also be used in certain count modes for storing

alternate count values and alternately counting the

load and hold register values to generate complex

waveforms.

Counter Outputs

Each of the counters has a single dedicated output

pin which is programmable for polarity, tri-state, low-Z

to ground and a variety of output modes as described

later. This flexibility allows operation in a variety of

bus and processor architectures.

Source Inputs

Each counter group may be programmed for a variety

of count sources including any of the five source

input lines, any of the internal prescaler outputs or

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