NCP51145 datasheet(2/6 Pages) ONSEMI

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NCP51145

www.onsemi.com

C1 = 1 to 100 nF Ceramic

C4 = 10

mF Ceramic

C2 = 10

mF Ceramic

R3 = Optional VTT Discharge Resistor

C3 = 1

N−Ch MOSFET = Optional Enable / Disable

Figure 1. Application Diagram

NCP51145

SO8−EP Package

PVCC

GND

VREF

VCC

VTT

5 V

100k

Enable

PVCC = 1.0 to 5.5 V*

VTT = 0.6 to 2.5 V*

2.2

*For DDR2: PVCC = 1.8 V, VTT = 0.9 V

DDR3: PVCC = 1.5 V, VTT = 0.75 V

DDR4: PVCC = 1.2 V, VTT = 0.60 V

PIN FUNCTION DESCRIPTION

Pin No.

SO8−EP

Pin No.

DFN8

Pin Name

Description

PVCC

Input voltage which supplies current to the output pin. CIN ^ ½ S COUT

GND

Common Ground

VREF

Buffered reference voltage input equal to

½ of VDDQ and active low shutdown pin. An

external resistor divider dividing down the PVCC voltage creates the regulated output

voltage. Pulling the pin to ground (0.15 V maximum) turns the device off.

VTT

Regulator output voltage capable of sourcing and sinking current while regulating the

output rail. COUT = 10 mF Ceramic, or greater

5, 7, 8

3, 7

True No Connect

VCC

The VCC pin is a 5 V input pin that provides internal bias to the controller. PVCC should

always be kept lower or equal to VCC.

−

VTTS

VTT Sense

EPAD

Pad for thermal connection. The exposed pad must be connected to the ground plane

using multiple vias for maximum power dissipation performance.

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