ST10F166 datasheet(45/62 Pages) STMICROELECTRONICS

45 / 62 page

ST10F166

45/62

AC Characteristics (Cont’d)

Multiplexed Bus for the ST10F166

CC =5 V

± 10 %;V

SS =0V

A = 0 to +70

°C

L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

ALE cycle time = 6 TCL + 2t

A + tC + tF (150 ns at 20-MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

=20 MHz

Variable CPU Clock

1/2TCL = 1 to 20 MHz

Uni

min.

max.

min.

max.

ALE high time

15 + t

–

TCL - 10 + t

–ns

Address setup to ALE

10 + t

–

TCL - 15 + t

–ns

Address hold after ALE

15 + t

–

TCL - 10 + t

–ns

ALE falling edge to RD, WR

(with RW-delay)

15 + t

–

TCL - 10 + t

–ns

ALE falling edge to RD, WR

(no RW-delay)

-10 + t

–

-10 + t

–ns

Address float after RD, WR

(with RW-delay)

t10

–

Address float after RD, WR

(no RW-delay)

t11

–

TCL + 5

RD, WR low time

(with RW-delay)

40 + t

–

2TCL - 10 + t

–ns

RD WR low time

(no RW-delay)

65 + t

–

3TCL - 10 + t

–ns

RD to valid data in

(with RW-delay)

–

30 + t

–

2TCL - 20

RD to valid data in

(no RW-delay)

t15

–

55 + tC

–

3TCL - 20

ALE low to valid data in

–

A +tC

–

3TCL - 20

A +tC

Address to valid data in

–

+2t

A +tC

–

4TCL - 25

+2t

A +tC

Data hold after RD

rising edge

–

Data float after RD

–

35 + t

–

2TCL - 15 + t

Data valid to WR

t22

35 + tC

–

2TCL - 15 + tC

–ns

Data hold after WR

35 + t

–

2TCL - 15 + t

–ns

ALE rising edge after RD, WR

35 + t

–

2TCL - 15 + t

–ns

Address hold after RD, WR

35 + t

–

2TCL - 15 + t

–ns

ST10F166 Datasheet(PDF) 45 Page - STMicroelectronics

ST10F166 Datasheet(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL