LPA2153–00

May.-2014

www.lowpowersemi.com

Page 2 of 13

Preliminary Datasheet

LPA2153

Pin Configuration

SD2

MODE2

EQ2

IN2

SD1

BYP1

IN1

MODE1

OUTN1

VDD1

OUTN2

OUTP2

BYP2

EQ1

VDD2

OUTP1

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

17

GND

Functional Pin Description

Pin

PIN No.

DESCRIPTION

SD2

1

Channel 2 Shutdown pin (active high).

MODE2

2

Channel 2 Mode control pin (High voltage with Class_D mode and low voltage

with Class_AB mode).

EQ2

3

Channel 2 EQ function pin(With resistor R4 and capacitor C4 in series between

IN2 and EQ, the high frequencies could be attenuated).

IN2

4

Channel 2 Input of amplifier.( With resistor R3 and capacitor C3 in series

between IN2 and signal, the low frequencies could be attenuated).

SD1

5

Channel 1 Shutdown pin (active high).

BYP1

6

Channel 1 Bypass pin (Connect a 0.22uF capacitor between this pin and GND).

EQ1

7

Channel 1 EQ function pin(With resistor R2 and capacitor C2 in series between

VIN and EQ, the high frequencies could be attenuated).

IN1

8

Channel 1 Input of amplifier.( With resistor R1 and capacitor C1 in series

between IN1 and signal, the low frequencies could be attenuated).

MODE1

9

Channel 1 Mode control pin (High voltage with Class_D mode and low voltage

with Class_AB mode).

OUTN1

10

Channel 1 Negative output of signal.

VDD1

11

Channel 1 Voltage supply pin.

OUTP1

12

Channel 1 Positive output of signal.

OUTN2

13

Channel 2 Negative output of signal.

VDD2

14

Channel 2 Voltage supply pin.

OUTP2

15

Channel 2 Positive output of signal.

BYP2

16

Channel 2 Bypass pin (Connect a 0.22uF capacitor between this pin and GND).

GND

17

Ground pin.