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EL7563CM Datasheet(PDF) 5 Page - Intersil Corporation

Part # EL7563CM
Description  Monolithic 4 Amp DC:DC Step-Down Regulator
PDF  16 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

EL7563CM Datasheet(HTML) 5 Page - Intersil Corporation

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5
FN7296.2
May 13, 2005
Pin Descriptions
20-PIN SO
(0.300”)
28-PIN
HTSSOP
PIN NAME
PIN FUNCTION
1
1
VREF
Bandgap reference bypass capacitor; typically 0.1µF to SGND
2
2
SGND
Control circuit negative supply or signal ground
3
3
COSC
Oscillator timing capacitor (see performance curves)
4
4
VDD
Control circuit positive supply; normally connected to VIN through an RC filter
5
5
VTJ
Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
6, 7
6, 7, 8, 9
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
8
10, 11
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
9
13
STP
Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2µA internal pull down current
10
14
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2µA internal pull up current
11, 12, 13
15, 16
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
14, 15
18, 19, 20, 21,
22, 23
LX
Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
16
24
VHI
Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF
capacitor
17
25
VDRV
Positive supply of low-side driver and input voltage for high side boot strap
18
26
PG
Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
19
27
FB
Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
20
28
EN
Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves (20 Pin SO Package)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
FIGURE 1. EL7563CM EFFICIENCY vs IO
FIGURE 2. EL7563CRE EFFICIENCY
VIN=3.3V
100
95
90
85
80
75
70
0
1
22.5
33.5
4
LOAD CURRENT IO (A)
0.5
1.5
VO=2.5V
VO=1V
VO=1.2V
VO=1.8V
VIN=3.3V
100
95
90
85
80
75
70
65
60
0.1
0.6
1.1
1.6
2.1
2.6
3.1
3.6
4
IO (A)
VO=2.5V
VO=1.2V
VO=1.8V
EL7563



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