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SIT9366 Datasheet(PDF) 1 Page - SiTime Corp. |
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SIT9366 Datasheet(HTML) 1 Page - SiTime Corp. |
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1 / 12 page ![]() SiT9366 1 to 220 MHz Ultra-low Jitter Differential Oscillator Features Any frequency between 1 MHz and 220 MHz accurate to 6 decimal places LVPECL, LVDS and HCSL output signaling 0.1ps RMS phase jitter (random) for Ethernet applications Contact SiTime for frequency stability as low as ±10 ppm Wide temperature range from -40°C to 85°C Contact SiTime for higher temperature range options Industry-standard packages: 3.2 x 2.5, 7.0 x 5.0 mm Contact SiTime for 5.0 x 3.2 mm package Applications 10/40/100GB Ethernet, SONET, SATA, SAS, Fibre Channel Telecom, networking, instrumentation, storage, servers Electrical Characteristics All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard output termination show in the termination diagrams. Typical values are at 25°C and nominal supply voltage. Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL Parameter Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f 1 – 220 MHz Accurate to 6 decimal places Frequency Stability Frequency Stability F_stab -10 – +10 ppm Inclusive of initial tolerance, operating temperature, rated power supply voltage and load variations. Contact SiTime for ± 10 ppm. -20 – +20 ppm Inclusive of initial tolerance, operating temperature, rated power supply voltage and load variations -25 – +25 ppm -50 – +50 ppm First Year Aging F_1y – ±1 – ppm At 25°C Temperature Range Operating Temperature Range T_use -20 – +70 °C Extended Commercial -40 – +85 °C Industrial. Contact SiTime for higher temperature range options Supply Voltage Supply Voltage Vdd 2.97 3.30 3.63 V 2.70 3.00 3.30 V 2.52 2.80 3.08 V 2.25 2.50 2.75 V Input Characteristics Input Voltage High VIH 70% – – Vdd Pin 1, OE Input Voltage Low VIL – – 30% Vdd Pin 1, OE Input Pull-up Impedance Z_in – 100 - kΩ Pin 1, OE logic high or logic low Output Characteristics Duty Cycle DC 45 – 55 % Startup and OE Timing Startup Time T_start – – 3.0 ms Measured from the time Vdd reaches its rated minimum value. OE Enable/Disable Time T_oe – – 3.8 µs f = 156.25 MHz. Rev 1.0 September 6, 2017 www.sitime.com |
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