MP2319

– 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2319 Rev.1.0

www.MonolithicPower.com

13

6/29/2016

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© 2016 MPS. All Rights Reserved.

Light-load operation is also called skip mode

because the HS-FET does not turn on as

frequently as it does in heavy-load conditions.

The frequency at which the HS-FET turns on is

a function of the output current. As the output

current increases, the time period that the

current modulator regulates becomes shorter,

and the HS-FET turns on more frequently. The

switching frequency increases in turn. The output

current reaches critical levels when the current

modulator time is zero, and can be determined

with Equation (1):

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2 L F

V





 



(1)

The device reverts to PWM mode once the

output

current

exceeds

the

critical

level.

Afterward, the switching frequency remains

fairly constant over the output current range.

Enable (EN)

EN is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator; drive EN low to turn off the

regulator. When floating, EN is pulled down to

GND by an internal 1.1M

Ω resistor. EN can be

input range.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP2319 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 3.85V,

while its falling threshold is 3.18V consistently.

Internal Soft Start (SS)

Soft start (SS) prevents the converter output

voltage

from

overshooting

during

start-up.

When the chip starts up, the internal circuitry

generates a soft-start voltage (SS) that ramps

up from 0V to 1.2V. When SS is lower than

REF, SS overrides REF so the error amplifier

uses SS as the reference. When SS exceeds

REF, the error amplifier uses REF as the

reference. The SS time is set to 0.8ms

internally.

Power Good (PG) Indicator

The MP2319 uses a power good (PG) output to

indicate whether the output voltage of the

module is ready or not. PG is an open-drain

output. Connect PG to VCC or another voltage

source through a pull-up resistor (e.g.:

100kΩ).

When input voltage is applied, PG is pulled

is pulled high after a 56µs delay. During normal

When UVLO or OTP occurs, PG is pulled low

immediately. When over-current (OC) occurs,

falls below 105% after over-voltage protection

(OVP), PG is pulled high after a 56µs delay.

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

The MP2319 has a valley limit control. During

the LS-FET on state, the inductor current is

monitored. When the sensed inductor current

reaches the valley current limit, the LS limit

comparator (shown in Figure 1) turns over, and

the MP2319 enters over-current protection

(OCP) mode. The HS-FET waits until the

inductor current falls below the valley current

limit before turning on again. Meanwhile, the

under-voltage (UV) threshold, typically 50%

below the reference. Once UV is triggered, the

MP2319 enters hiccup mode to restart the part

periodically.

During OCP, the device attempts to recover

from the over-current fault with hiccup mode.

The MP2319 disables the output power stage,

discharges the soft-start cap, and then tries to

soft-start

automatically.

If

the

over-current

condition still remains after the soft-start ends,

the MP2319 repeats this operation cycle until

the over-current condition is removed, and then

the output rises back to regulation levels. OCP

is a non-latch protection.