MP8714 – 17V, 10A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8714 Rev.1.0

www.MonolithicPower.com

16

12/27/2016

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© 2016 MPS. All Rights Reserved.

For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current.

The

input

capacitor can

be

electrolytic,

tantalum, or ceramic. When using electrolytic or

tantalum capacitors, add a small, high-quality

ceramic capacitor (e.g.: 0.1μF) as close to the

IC as possible. When using ceramic capacitors,

ensure that they have enough capacitance to

provide sufficient charge to prevent excessive

voltage ripple at the input. The input voltage

ripple caused by capacitance can be estimated

with Equation (7):

LOAD

OUT

OUT

IN

IN

SIN

IV

V

V1

fC1

V

V







 







(7)

Selecting the Output Capacitor

The output capacitor (C2) maintains the DC

output voltage. Use ceramic, tantalum, or low-

ESR electrolytic capacitors. For best results,

use low ESR capacitors to keep the output

voltage ripple low. The output voltage ripple can

be estimated with Equation (8):

OUT

OUT

OUT

ESR

S1

IN

S

VV

1

V1

R

fL

V

8 f

C2







 









 

  (8)

equivalent series resistance (ESR) value of the

output capacitor.

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency, and the capacitance causes the

majority of the output voltage ripple. For

simplification, the output voltage ripple can be

estimated with Equation (9):

OUT

OUT

OUT

2

IN

S1

VV

∆V1

V

8f

L

C2



 



 



(9)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated by Equation (10):

OUT

OUT

OUT

ESR

IN

S1

VV

∆V1

R

fL

V



 









(10)

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP8714 can be optimized for a wide range of

capacitance and ESR values.

Efficient PCB layout is critical for stable

operation. A four-layer layout is strongly

recommended

to

achieve

better

thermal

performance. For best results, refer to Figure 7

and follow the guidelines below.

1. Place the high current paths (PGND, VIN,

and SW) very close to the device with short,

direct, and wide traces.

2. Keep the VIN and GND pads connected

with large copper traces.

3. Use at least two layers for the VIN and GND

trace to achieve better thermal performance.

4. Add several vias close to the VIN and GND

pads to help with thermal dissipation.

5. Place the input capacitors as close to VIN

and GND as possible.

6. Place the decoupling capacitor as close to

VCC and GND as possible.

7. Place the external feedback resistors next

to FB.

8. Ensure that there is no via on the FB trace.

9. Keep the switching node SW short and

away from the feedback network.

10. Keep the BST voltage path (BST, C5, and

SW) as short as possible.

NOTE:

10) The recommended layout is based on the Typical Application

circuit on page 18.