SAF-C161RI datasheet(9/60 Pages) SIEMENS

9 / 60 page

Semiconductor Group

1998-05-01

C161RI

PORT0:

P0L.0 –

P0L.7,

P0H.0 -

P0H.7

38 –

45,

48 –

40 –

47,

50 –

I/O

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of external bus configurations, PORT0 serves as the

address (A) and address/data (AD) bus in multiplexed bus

modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width:

8-bit

16-bit

P0L.0 – P0L.7:

D0 – D7

D0 - D7

P0H.0 – P0H.7:

I/O

D8 - D15

Multiplexed bus modes:

Data Path Width:

8-bit

16-bit

P0L.0 – P0L.7:

AD0 – AD7

AD0 - AD7

P0H.0 – P0H.7:

A8 - A15

AD8 - AD15

PORT1:

P1L.0 –

P1L.7,

P1H.0 -

P1H.7

56 –

63,

66 –

58 -

65,

68 -

I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the 16-

bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

RSTIN

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin for a specified duration while the oscillator is

running resets the C161RI. An internal pullup resistor permits

power-on reset using only a capacitor connected to

SS.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon a

software reset, a WDT reset and a hardware reset. 1)

RSTOUT 77

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C161RI to go into power

down mode. If NMI is high, when PWRDN is executed, the

part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

Pin Definitions and Functions (cont’d)

Symbol

Pin No.

TQFP

Pin No.

MQFP

Input

Outp

Function

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