MPQ1530

– TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED

MPQ1530 Rev. 1.02

www.MonolithicPower.com

12

7/14/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

With all boost regulators the right half plane

zero (RHPZ) is given in hertz by:

1

L

I

2

V

V

V

f

LOAD

MAIN

2

MAIN

IN

RHPZ























Error Amplifier Compensation

To stabilize the feedback loop dynamics the

error amplifier compensation is as follows:

3

C

10

2

1

f

6

1

POLE









3

C

3

R

2

1

f

1

ZERO









Where R3 and C3 are part of the compensation

network in Figure 3. A 6.8k

Ω and 10nF

combination gives about 70

 of phase margin

and bandwidth of about 35kHz for most load

conditions.

Linear Regulator Compensation

The

positive

and

negative

regulators

are

controlled by a transconductance amplifier and

a pass transistor. The DC gain of either LDO is

approximately 100dB with a slight dependency

pole.

LDO

LOAD

1

LDOPOLE

C

R

2

1

f









The pass transistor’s internal pole is about

100Hz to 300Hz. To compensate for the two

pole system and add more phase and gain

margin, a capacitor network can be added in

parallel with the high-side resistor.

For the positive linear regulator:

7

C

8

R

9

R

2

1

f

1

POSPOLE









7

C

9

R

2

1

f

1

POSZERO









For the negative linear regulator:

9

C

5

R

7

R

2

1

f

1

NEGPOLE









9

C

7

R

2

1

f

1

NEGZERO









out the zero created by the equivalent series

LDO

LDOESR

LDOZERO

C

R

2

1

f









For the component values shown in Figure 3, a

330pF capacitor provides about 30

 of phase

margin and a bandwidth of approximately

90kHz on both regulators.

Layout Considerations

Careful

PC

board

layout

is

important

to

minimize ground bounce and noise. First, place

the main boost converter inductor, output diode

and output capacitor as close to the SW and

PGND pins as possible with wide traces. Then

place ceramic bypass capacitors near IN, IN2

and IN3 pins to the PGND pin. Keep the

charge-pump circuitry close to the IC with wide

traces. Place all FB resistive dividers close to

their respective FB pins. Separate GND and

PGND areas and connect them at one point as

close to the IC as possible. Avoid having

sensitive traces near the SW node and high

current lines. Refer to the MPQ1530 demo

board for an example of proper board layout.